[coreboot-gerrit] New patch to review for coreboot: pcengines/apu1: Fix SPD for 4GB model

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11899

-gerrit

commit 2aaa0b3f1e0e6c9e4096b7547c042fa6727edcb4
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Wed Oct 14 16:03:56 2015 +0300

    pcengines/apu1: Fix SPD for 4GB model
    
    Value of tRFCmin was incorrectly using 2 Gigabit chip data.
    There was no observed instability or bug reports because of this.
    
    Change-Id: Ifa03b883afa5a304dd20caf3d4d0383c6cfebdb8
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex b/src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex
index 4af1bf8..876ee64 100644
--- a/src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex
+++ b/src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex
@@ -127,7 +127,8 @@
 # 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
 # 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
 #    0x500 = 160ns - for 2 Gigabit chips
-00 05
+#    0x820 = 260ns - for 4 Gigabit chips
+20 08
 
 # 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
 #    0x3c = 7.5 ns - All DDR3 SDRAM speed bins