[coreboot-gerrit] Patch set updated for coreboot: soc/intel/broadwell: fix USBDEBUG copy-pasta

[Georg Wicherski (gw@oxff.net)]

Georg Wicherski (gw at oxff.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11874

-gerrit

commit d53c10072efc8318c69a7dba7acc47918679457e
Author: Georg Wicherski <gw at oxff.net>
Date:   Tue Oct 13 16:27:15 2015 +0200

    soc/intel/broadwell: fix USBDEBUG copy-pasta
    
    The broadwell soc code was upstreamed based off an old coreboot branch
    and apparently never tested with USBDEBUG.
    This changeset fixes USBDEBUG on the not yet upstreamed Auron-Paine
    board, as verified with a FT232H setup. The fix is simply removing
    outdated code that since branching off had been deduplicated in upstream
    coreboot, anyway.
    
    Change-Id: I53c924aa2a5357ed8313d0c9eaa2f9f9e132345e
    Signed-off-by: Georg Wicherski <gwicherski at gmail.com>
---
 src/soc/intel/broadwell/Makefile.inc |  6 -----
 src/soc/intel/broadwell/cpu.c        | 14 ----------
 src/soc/intel/broadwell/ehci.c       | 24 +----------------
 src/soc/intel/broadwell/usbdebug.c   | 51 ------------------------------------
 4 files changed, 1 insertion(+), 94 deletions(-)

diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index a9004ac..e10704b 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -66,12 +66,6 @@ smm-y      += xhci.c
 
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
-ifeq ($(CONFIG_USBDEBUG),y)
-ramstage-y += usbdebug.c
-romstage-y += usbdebug.c
-smm-y      += usbdebug.c
-endif
-
 cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin
 
 CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index f3ab30a..2580ef9 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -574,27 +574,13 @@ static void configure_mca(void)
 		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
 }
 
-#if CONFIG_USBDEBUG
-static unsigned ehci_debug_addr;
-#endif
-
 static void bsp_init_before_ap_bringup(struct bus *cpu_bus)
 {
-#if CONFIG_USBDEBUG
-	if(!ehci_debug_addr)
-		ehci_debug_addr = get_ehci_debug();
-	set_ehci_debug(0);
-#endif
-
 	/* Setup MTRRs based on physical address size. */
 	x86_setup_fixed_mtrrs();
 	x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2);
 	x86_mtrr_check();
 
-#if CONFIG_USBDEBUG
-	set_ehci_debug(ehci_debug_addr);
-#endif
-
 	initialize_vr_config();
 	calibrate_24mhz_bclk();
 	configure_pch_power_sharing();
diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c
index d22fcae..89f1521 100644
--- a/src/soc/intel/broadwell/ehci.c
+++ b/src/soc/intel/broadwell/ehci.c
@@ -48,28 +48,6 @@ static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned devic
 	pci_write_config8(dev, 0x80, access_cntl);
 }
 
-static void usb_ehci_set_resources(struct device *dev)
-{
-#if CONFIG_USBDEBUG
-	struct resource *res;
-	u32 base;
-	u32 usb_debug;
-
-	usb_debug = get_ehci_debug();
-	set_ehci_debug(0);
-#endif
-	pci_dev_set_resources(dev);
-
-#if CONFIG_USBDEBUG
-	res = find_resource(dev, 0x10);
-	set_ehci_debug(usb_debug);
-	if (!res) return;
-	base = res->base;
-	set_ehci_base(base);
-	report_resource_stored(dev, res, "");
-#endif
-}
-
 static void ehci_enable(struct device *dev)
 {
 	if (CONFIG_USBDEBUG)
@@ -84,7 +62,7 @@ static struct pci_operations ehci_ops_pci = {
 
 static struct device_operations usb_ehci_ops = {
 	.read_resources		= &pci_dev_read_resources,
-	.set_resources		= &usb_ehci_set_resources,
+	.set_resources		= &pci_dev_set_resources,
 	.enable_resources	= &pci_dev_enable_resources,
 	.ops_pci		= &ehci_ops_pci,
 	.enable			= &ehci_enable,
diff --git a/src/soc/intel/broadwell/usbdebug.c b/src/soc/intel/broadwell/usbdebug.c
deleted file mode 100644
index dcd8761..0000000
--- a/src/soc/intel/broadwell/usbdebug.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <usbdebug.h>
-#include <device/pci.h>
-#include <device/pci_def.h>
-#include <soc/pci_devs.h>
-
-void set_debug_port(unsigned int port)
-{
-	/* Hardcoded to physical port 1 */
-}
-
-void enable_usbdebug(unsigned int port)
-{
-	u32 tmp32;
-
-	tmp32 = pci_read_config32(PCH_DEV_EHCI, PCI_VENDOR_ID);
-	if (tmp32 == 0xffffffff || tmp32 == 0)
-		return;
-
-	/* Set the EHCI BAR address. */
-	pci_write_config32(PCH_DEV_EHCI, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
-
-	/* Enable access to the EHCI memory space registers. */
-	pci_write_config8(PCH_DEV_EHCI, PCI_COMMAND, PCI_COMMAND_MEMORY);
-
-	/* Force ownership of the Debug Port to the EHCI controller. */
-	tmp32 = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
-	tmp32 |= (1 << 30);
-	write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, tmp32);
-}