[coreboot-gerrit] Patch merged into coreboot/master: intel: update common and FSP cache-as-ram parameters

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit e1ecfc93af4918c2a9a4647cf550cb7ecc2b92d6
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Sep 16 15:18:04 2015 -0500

    intel: update common and FSP cache-as-ram parameters
    
    Instead of just passing bits, tsc_low, tsc_high, and an
    opaque pointer to chipset context those fields are bundled
    into a cache_as_ram_params struct. Additionally, a new
    struct fsp_car_context is created to hold the FSP
    information. These could be combined as the existing
    romstage code assumes what the chipset_context values are, but
    I'm leaving the concept of "common" alone for the time being.
    While working in that area the ABI between assembly and C code
    has changed to just pass a single pointer to cache_as_ram_params
    struct. Lastly, validate the bootloader cache-as-ram region
    with the Kconfig options.
    
    BUG=chrome-os-partner:44676
    BRANCH=None
    TEST=Built and booted glados.
    
    Original-Change-Id: Ib2a0e38477ef7c15cff1836836cfb55e5dc8a58e
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/300190
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy at intel.com>
    
    Change-Id: Ic5a0daa4e2fe5eda0c4d2a45d86baf14ff7b2c6c
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11809
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11809 for details.

-gerrit