[coreboot-gerrit] Patch set updated for coreboot: AMD Bettong: refactor PCI interrupt table
WANG Siyuan (wangsiyuanbuaa@gmail.com)
gerrit at coreboot.org
Sun Oct 11 18:53:55 CET 2015
WANG Siyuan (wangsiyuanbuaa at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11746
-gerrit
commit 7caed6a9b78aba5e9a8326846513e7a36a10f2ba
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date: Tue Aug 18 06:22:22 2015 +0800
AMD Bettong: refactor PCI interrupt table
1. Use write_pci_int_table to write registers 0xC00/0xC01.
2. Add GPIO, I2C and UART interrupt according
"BKDG for AMD Family 15h Models 60h-6Fh Processors",
50742 Rev 3.01 - July 17, 2015
3. The interrupt valudes are copied from bettong/mptable.c.
All devices work in Windows 10.
Change-Id: Iad13bc02c84a5dfc7c24356436ac560f593304d7
Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
---
src/mainboard/amd/bettong/mainboard.c | 62 +++++++++++++++++++++++
src/mainboard/amd/bettong/mptable.c | 54 +++++---------------
src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | 8 ++-
src/southbridge/amd/pi/hudson/amd_pci_int_types.h | 3 +-
4 files changed, 84 insertions(+), 43 deletions(-)
diff --git a/src/mainboard/amd/bettong/mainboard.c b/src/mainboard/amd/bettong/mainboard.c
index 6212665..9669b8c 100644
--- a/src/mainboard/amd/bettong/mainboard.c
+++ b/src/mainboard/amd/bettong/mainboard.c
@@ -21,6 +21,65 @@
#include <device/device.h>
#include <arch/acpi.h>
#include <agesawrapper.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+/***********************************************************
+ * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
+ * This table is responsible for physically routing the PIC and
+ * IOAPIC IRQs to the different PCI devices on the system. It
+ * is read and written via registers 0xC00/0xC01 as an
+ * Index/Data pair. These values are chipset and mainboard
+ * dependent and should be updated accordingly.
+ *
+ * These values are used by the PCI configuration space,
+ * MP Tables. TODO: Make ACPI use these values too.
+ */
+const u8 mainboard_picr_data[] = {
+ [0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,
+ [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,
+ [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
+ [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x30] = 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,
+ [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x40] = 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x50] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F,
+ [0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+ [0x60] = 0x1F,0x1F,0x07,0x1F,0x1F,0x1F,0x1F,0x1F,
+ [0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+ [0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,
+ [0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+};
+
+const u8 mainboard_intr_data[] = {
+ [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
+ [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10,
+ [0x18] = 0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,
+ [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
+ [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,
+ [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x50] = 0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,
+ [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x60] = 0x1F,0x1F,0x07,0x00,0x00,0x00,0x00,0x00,
+ [0x68] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ [0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,
+ [0x78] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+ intr_data_ptr = mainboard_intr_data;
+ picr_data_ptr = mainboard_picr_data;
+}
+
+
/*************************************************
* enable the dedicated function in bettong board.
@@ -31,6 +90,9 @@ static void bettong_enable(device_t dev)
if (acpi_is_wakeup_s3())
agesawrapper_fchs3earlyrestore();
+
+ /* Initialize the PIRQ data structures for consumption */
+ pirq_setup();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c
index ede8f7a..99ac4e0 100644
--- a/src/mainboard/amd/bettong/mptable.c
+++ b/src/mainboard/amd/bettong/mptable.c
@@ -28,23 +28,7 @@
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include "southbridge/amd/pi/hudson/hudson.h" /* pm_ioread() */
-
-u8 picr_data[0x54] = {
- 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x03,0x04,0x05,0x07
-};
-u8 intr_data[0x54] = {
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
- 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
-};
+#include <southbridge/amd/common/amd_pci_util.h>
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
{
@@ -68,7 +52,6 @@ static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
- u8 byte;
/*
* By the time this function gets called, the IOAPIC registers
@@ -95,17 +78,6 @@ static void *smp_write_config_table(void *v)
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
- /* PIC IRQ routine */
- for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
- outb(byte, 0xC00);
- outb(picr_data[byte], 0xC01);
- }
-
- /* APIC IRQ routine */
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
- outb(byte | 0x80, 0xC00);
- outb(intr_data[byte], 0xC01);
- }
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
@@ -119,27 +91,27 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* Internal VGA */
- PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
- PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
- PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
- PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
- PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
- PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
- PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
/* sata */
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
- PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
/* on board NIC & Slot PCIE. */
diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
index a1e5e07..dfdd67c 100644
--- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
+++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h
@@ -81,8 +81,14 @@
#endif
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
-#define FCH_INT_TABLE_SIZE 0x75
+#define FCH_INT_TABLE_SIZE 0x76
#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */
+#define PIRQ_I2C0 0x70
+#define PIRQ_I2C1 0x71
+#define PIRQ_I2C2 0x72
+#define PIRQ_I2C3 0x73
+#define PIRQ_UART0 0x74
+#define PIRQ_UART1 0x75
#endif
#endif /* AMD_PCI_INT_DEFS_H */
diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
index b48f87e..e8cb6fa 100644
--- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
+++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h
@@ -36,7 +36,8 @@ const char * intr_types[] = {
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)
[0x40] = "IDE\t", "SATA\t",
[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
- [0x75] = NULL
+ [0x62] = "GPIO\t",
+ [0x70] = "I2C0\t", "I2C1\t", "I2C2\t","I2C3\t", "UART0\t", "UART1\t",
#endif
};
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