[coreboot-gerrit] New patch to review for coreboot: Kill lvds_num_lanes
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Sun Oct 11 11:15:33 CEST 2015
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11862
-gerrit
commit 60b91e11972c962df628f8695019a1892e8ce928
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Sun Oct 11 02:05:55 2015 +0200
Kill lvds_num_lanes
Only one value would work with corresponding gma code currently (which one
depends on board). Going forward, it's possible to compute which number can
be used, so there is no need to keep this info around.
Change-Id: Iadc77ef94b02f892860e3ae8d70a0a792758565d
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/drivers/intel/gma/i915.h | 1 -
src/mainboard/lenovo/t400/devicetree.cb | 1 -
src/mainboard/lenovo/t420s/devicetree.cb | 1 -
src/mainboard/lenovo/t430s/devicetree.cb | 1 -
src/mainboard/lenovo/t520/devicetree.cb | 1 -
src/mainboard/lenovo/t530/devicetree.cb | 1 -
src/mainboard/lenovo/x200/devicetree.cb | 1 -
src/mainboard/lenovo/x201/devicetree.cb | 1 -
src/mainboard/lenovo/x220/devicetree.cb | 1 -
src/mainboard/lenovo/x230/devicetree.cb | 1 -
src/mainboard/packardbell/ms2290/devicetree.cb | 1 -
src/northbridge/intel/gm45/gma.c | 2 +-
src/northbridge/intel/nehalem/gma.c | 2 +-
src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c | 2 +-
src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c | 2 +-
util/autoport/sandybridge.go | 5 -----
16 files changed, 4 insertions(+), 20 deletions(-)
diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h
index ed6c23b..35f9c25 100644
--- a/src/drivers/intel/gma/i915.h
+++ b/src/drivers/intel/gma/i915.h
@@ -289,7 +289,6 @@ struct i915_gpu_controller_info
{
int use_spread_spectrum_clock;
int link_frequency_270_mhz;
- int lvds_num_lanes;
u32 backlight;
int ndid;
u32 did[5];
diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
index cf6157c..af92d30 100644
--- a/src/mainboard/lenovo/t400/devicetree.cb
+++ b/src/mainboard/lenovo/t400/devicetree.cb
@@ -5,7 +5,6 @@ chip northbridge/intel/gm45
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1"
- register "gfx.lvds_num_lanes" = "4"
device cpu_cluster 0 on
chip cpu/intel/socket_BGA956
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index 9dd32c0..ca02455 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1"
- register "gfx.lvds_num_lanes" = "4"
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610"
diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb
index e94fcb3..7b83fbc 100644
--- a/src/mainboard/lenovo/t430s/devicetree.cb
+++ b/src/mainboard/lenovo/t430s/devicetree.cb
@@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1"
- register "gfx.lvds_num_lanes" = "1"
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x11551155"
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index d23a648..379a95d 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -15,7 +15,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1"
- register "gfx.lvds_num_lanes" = "4"
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610"
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index 1ead01c..7db65c7 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -15,7 +15,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1"
- register "gfx.lvds_num_lanes" = "1"
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x11551155"
diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb
index 007141c..36a1939 100644
--- a/src/mainboard/lenovo/x200/devicetree.cb
+++ b/src/mainboard/lenovo/x200/devicetree.cb
@@ -5,7 +5,6 @@ chip northbridge/intel/gm45
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1"
- register "gfx.lvds_num_lanes" = "4"
device cpu_cluster 0 on
chip cpu/intel/socket_BGA956
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index 0a42a53..0b53e22 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -39,7 +39,6 @@ chip northbridge/intel/nehalem
register "gpu_pch_backlight" = "0x061a061a"
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1"
- register "gfx.lvds_num_lanes" = "4"
chip ec/lenovo/pmh7
device pnp ff.1 on # dummy
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index 6e9054a..9c9ac7c 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -15,7 +15,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1"
- register "gfx.lvds_num_lanes" = "4"
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610"
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index 25367c8..37d53d4 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -15,7 +15,6 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1"
- register "gfx.lvds_num_lanes" = "1"
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x11551155"
diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb
index 5ca123e..54fd8ae 100644
--- a/src/mainboard/packardbell/ms2290/devicetree.cb
+++ b/src/mainboard/packardbell/ms2290/devicetree.cb
@@ -39,7 +39,6 @@ chip northbridge/intel/nehalem
register "gpu_pch_backlight" = "0x061a061a"
register "gfx.use_spread_spectrum_clock" = "0"
register "gfx.link_frequency_270_mhz" = "1"
- register "gfx.lvds_num_lanes" = "4"
device cpu_cluster 0 on
chip cpu/intel/model_2065x
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 33eae84..3dd051c 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -244,7 +244,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
- / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4));
+ / (link_frequency * 8 * 4);
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive);
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index ed993f1..c4e7731 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -792,7 +792,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
- / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4));
+ / (link_frequency * 8 * 4);
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive);
diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
index 7cb71f3..c37959e 100644
--- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
@@ -313,7 +313,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
link_m1 = ((uint64_t)link_n1 * edid.mode.pixel_clock) / link_frequency;
data_m1 = ((uint64_t)data_n1 * 18 * edid.mode.pixel_clock)
- / (link_frequency * 8 * (info->lvds_num_lanes ? : 1));
+ / (link_frequency * 8);
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive);
diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
index 9b2f1f2..cd48174 100644
--- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
@@ -276,7 +276,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
- / (link_frequency * 8 * (info->lvds_num_lanes ? : 4));
+ / (link_frequency * 8 * 4);
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive);
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go
index 227c111..a2afc6c 100644
--- a/util/autoport/sandybridge.go
+++ b/util/autoport/sandybridge.go
@@ -16,13 +16,9 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
pchLVDS := inteltool.IGD[0xe1180]
dualChannel := pchLVDS&(3<<2) == (3 << 2)
pipe := (pchLVDS >> 30) & 1
- data_m1 := inteltool.IGD[0x60030+0x1000*pipe] & 0xffffff
- data_n1 := inteltool.IGD[0x60034+0x1000*pipe]
link_m1 := inteltool.IGD[0x60040+0x1000*pipe]
link_n1 := inteltool.IGD[0x60044+0x1000*pipe]
- data_factor := float32(data_m1) / float32(data_n1)
link_factor := float32(link_m1) / float32(link_n1)
- num_lanes := uint32((link_factor/data_factor)*18.0/8.0 + 0.5)
fp0 := inteltool.IGD[0xc6040+8*pipe]
dpll := inteltool.IGD[0xc6014+4*pipe]
pixel_m2 := fp0 & 0xff
@@ -54,7 +50,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
"gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]),
"gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
"gfx.use_spread_spectrum_clock": FormatBool((inteltool.IGD[0xc6200]>>12)&1 != 0),
- "gfx.lvds_num_lanes": FormatInt32(num_lanes),
"gfx.link_frequency_270_mhz": FormatBool(link_frequency > 200000),
/* FIXME:XX hardcoded. */
"gfx.ndid": "3",
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