[coreboot-gerrit] Patch set updated for coreboot: Braswell: Modify CB to accomodate new FSPv83

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11813

-gerrit

commit aecd13d6b1293361e03409d64975ed9551712530
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Fri Aug 7 18:22:54 2015 +0530

    Braswell: Modify CB to accomodate new FSPv83
    
    Latest FSPv83 made some change related to UPD/VPD
    need this patch to align those
    
    BUG=None
    TEST=Build and Boot Cyan System
    BRANCH=strago-7287.B
    CQ-DEPEND=CL:*226897
    
    Original-Change-Id: I6395f3a1f4eecaef14fc4720b00252f9e6143fa3
    Original-Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/291394
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Tested-by: Hannah Williams <hannah.williams at intel.com>
    Original-Commit-Queue: Hannah Williams <hannah.williams at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/303137
    Original-Commit-Ready: John Zhao <john.zhao at intel.com>
    Original-Tested-by: John Zhao <john.zhao at intel.com>
    
    Change-Id: I9920eea84b802699454850bfde489668201ffeb6
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/braswell/chip.c | 14 ++++++--------
 src/soc/intel/braswell/chip.h |  2 --
 src/soc/intel/common/vbt.c    |  2 +-
 3 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index 6f22740..822ee78 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -96,7 +96,6 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	params->PcdEnableHsuart0 = config->PcdEnableHsuart0;
 	params->PcdEnableHsuart1 = config->PcdEnableHsuart1;
 	params->PcdEnableAzalia = config->PcdEnableAzalia;
-	params->AzaliaConfigPtr = config->AzaliaConfigPtr;
 	params->PcdEnableSata = config->PcdEnableSata;
 	params->PcdEnableXhci = config->PcdEnableXhci;
 	params->PcdEnableLpe = config->PcdEnableLpe;
@@ -109,7 +108,8 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	params->PcdEnableI2C4 = config->PcdEnableI2C4;
 	params->PcdEnableI2C5 = config->PcdEnableI2C5;
 	params->PcdEnableI2C6 = config->PcdEnableI2C6;
-	params->PcdGraphicsConfigPtr = config->PcdGraphicsConfigPtr;
+	params->GraphicsConfigPtr = 0;
+	params->AzaliaConfigPtr = 0;
 	params->PunitPwrConfigDisable = config->PunitPwrConfigDisable;
 	params->ChvSvidConfig = config->ChvSvidConfig;
 	params->DptfDisable = config->DptfDisable;
@@ -171,11 +171,9 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
 		new->PcdEnableHsuart1);
 	soc_display_upd_value("PcdEnableAzalia", 1, old->PcdEnableAzalia,
 		new->PcdEnableAzalia);
-	soc_display_upd_value("AzaliaVerbTablePtr", 4,
-		(uint32_t)old->AzaliaVerbTablePtr,
-		(uint32_t)new->AzaliaVerbTablePtr);
-	soc_display_upd_value("AzaliaConfigPtr", 4, old->AzaliaConfigPtr,
-		new->AzaliaConfigPtr);
+	soc_display_upd_value("AzaliaConfigPtr", 4,
+			(uint32_t)old->AzaliaConfigPtr,
+			(uint32_t)new->AzaliaConfigPtr);
 	soc_display_upd_value("PcdEnableSata", 1, old->PcdEnableSata,
 		new->PcdEnableSata);
 	soc_display_upd_value("PcdEnableXhci", 1, old->PcdEnableXhci,
@@ -201,7 +199,7 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
 	soc_display_upd_value("PcdEnableI2C6", 1, old->PcdEnableI2C6,
 		new->PcdEnableI2C6);
 	soc_display_upd_value("PcdGraphicsConfigPtr", 4,
-		old->PcdGraphicsConfigPtr, new->PcdGraphicsConfigPtr);
+		old->GraphicsConfigPtr, new->GraphicsConfigPtr);
 	soc_display_upd_value("GpioFamilyInitTablePtr", 4,
 		(uint32_t)old->GpioFamilyInitTablePtr,
 		(uint32_t)new->GpioFamilyInitTablePtr);
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index ff68014..e415dfd 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -85,7 +85,6 @@ struct soc_intel_braswell_config {
 	UINT8  PcdEnableHsuart0;
 	UINT8  PcdEnableHsuart1;
 	UINT8  PcdEnableAzalia;
-	UINT32 AzaliaConfigPtr;
 	UINT8  PcdEnableSata;
 	UINT8  PcdEnableXhci;
 	UINT8  PcdEnableLpe;
@@ -98,7 +97,6 @@ struct soc_intel_braswell_config {
 	UINT8  PcdEnableI2C4;
 	UINT8  PcdEnableI2C5;
 	UINT8  PcdEnableI2C6;
-	UINT32 PcdGraphicsConfigPtr;
 	UINT8  PunitPwrConfigDisable;
 	UINT8  ChvSvidConfig;
 	UINT8  DptfDisable;
diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c
index b12ec04..3aba7c7 100644
--- a/src/soc/intel/common/vbt.c
+++ b/src/soc/intel/common/vbt.c
@@ -47,5 +47,5 @@ void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params)
 		} else
 			vbt_data = NULL;
 	}
-	params->PcdGraphicsConfigPtr = (u32)vbt_data;
+	params->GraphicsConfigPtr = (u32)vbt_data;
 }