[coreboot-gerrit] Patch set updated for coreboot: skylake: Leave SPI controller enabled
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Fri Oct 9 21:57:18 CET 2015
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11825
-gerrit
commit 0c6e24d8df65447982fecf2af179800008dfe408
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Thu Sep 17 11:53:27 2015 -0700
skylake: Leave SPI controller enabled
Leave the SPI controller enabled upon boot block exit.
BRANCH=none
BUG=chrome-os-partner:44827
TEST=Build and run on kunimitsu
Change-Id: I5b10d7cc8d5d350282206abe6a945bab66f97ada
Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
---
src/soc/intel/skylake/bootblock/cpu.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index 6c5ab4f..979a5a8 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -118,11 +118,6 @@ static void set_pch_cpu_strap(u8 flex_ratio)
ssl = read32(spibar + SPIBAR_RESET_LOCK);
ssl |= SPIBAR_RESET_LOCK_ENABLE;
write32(spibar + SPIBAR_RESET_LOCK, ssl);
-
- /* Disable SPI Controller MMIO space */
- pcireg = pci_read_config8(dev, PCI_COMMAND);
- pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
- pci_write_config8(dev, PCI_COMMAND, pcireg);
}
static void set_flex_ratio_to_tdp_nominal(void)
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