[coreboot-gerrit] New patch to review for coreboot: intel fsp1_1: prepare for romstage vboot verification split
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Thu Oct 8 17:12:42 CET 2015
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11816
-gerrit
commit beccc66ddde153cb5f5a09a6ea9b49fee9b43f47
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Sep 24 12:26:31 2015 -0500
intel fsp1_1: prepare for romstage vboot verification split
In order to introduce a verstage which performs vboot
verification the cache-as-ram environment needs to be
generalized and split into pieces that can be utilized
in romstage and/or verstage. Therefore, the romstage
pieces were removed from the cache-as-ram specific pieces
that are generic:
- Add fsp/car.h to house the declarations for functions in
the cache-as-ram environment
- Only have cache_as_ram_params which are isolated form the
cache-as-ram environment aside from FSP_INFO_HEADER.
- Hardware requirements for console initialization is done
in the cache-as-ram specific files.
- Provide after_raminit.S which can be included from a
romstage separated from cache-as-ram as well as one that
is tightly coupled to the cache-as-ram environment.
- Update the fallout from the API changes in
soc/intel/{braswell,common,skylake}.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a
Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302481
Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/drivers/intel/fsp1_1/Makefile.inc | 1 +
src/drivers/intel/fsp1_1/after_raminit.S | 153 ++++++++++++++++++++++++++++
src/drivers/intel/fsp1_1/cache_as_ram.inc | 137 +------------------------
src/drivers/intel/fsp1_1/car.c | 85 ++++++++++++++++
src/drivers/intel/fsp1_1/include/fsp/car.h | 52 ++++++++++
src/drivers/intel/fsp1_1/include/fsp/util.h | 7 --
src/mainboard/google/cyan/com_init.c | 2 +-
src/mainboard/intel/strago/com_init.c | 2 +-
src/soc/intel/braswell/romstage/romstage.c | 12 +--
src/soc/intel/common/raminit.c | 4 +-
src/soc/intel/common/romstage.c | 73 ++-----------
src/soc/intel/common/romstage.h | 14 +--
src/soc/intel/skylake/romstage/romstage.c | 20 ++--
13 files changed, 321 insertions(+), 241 deletions(-)
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index bab68e1..78e1006 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -18,6 +18,7 @@
# Foundation, Inc.
#
+romstage-y += car.c
romstage-y += fsp_util.c
romstage-y += hob.c
diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S
new file mode 100644
index 0000000..2cc4ef3
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/after_raminit.S
@@ -0,0 +1,153 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+
+/*
+ * This is the common entry point after DRAM has been initialized.
+ */
+ /*
+ * eax: New stack address
+ * ebx: FSP_INFO_HEADER address
+ */
+
+ /* Switch to the stack in RAM */
+ movl %eax, %esp
+
+ /* Calculate TempRamExit entry into FSP */
+ movl %ebx, %ebp
+ mov 0x40(%ebp), %eax
+ add 0x1c(%ebp), %eax
+
+ /* Build the call frame */
+ pushl $0
+
+ /* Call TempRamExit */
+ call *%eax
+ add $4, %esp
+ cmp $0, %eax
+ jz 1f
+ /*
+ * Failures for post code BC - failed in TempRamExit
+ *
+ * 0x00 - FSP_SUCCESS: Temp RAM Exit completed successfully.
+ * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
+ * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
+ * 0x07 - FSP_DEVICE_ERROR: Temp RAM Exit failed.
+ */
+ movb $0xBC, %ah
+ jmp .Lhlt
+
+1:
+ /* Display the MTRRs */
+ call soc_display_mtrrs
+
+ /*
+ * The stack contents are initialized in src/soc/intel/common/stack.c
+ * to be the following:
+ *
+ * *
+ * *
+ * *
+ * +36: MTRR mask 1 63:32
+ * +32: MTRR mask 1 31:0
+ * +28: MTRR base 1 63:32
+ * +24: MTRR base 1 31:0
+ * +20: MTRR mask 0 63:32
+ * +16: MTRR mask 0 31:0
+ * +12: MTRR base 0 63:32
+ * +8: MTRR base 0 31:0
+ * +4: Number of MTRRs to setup (described above)
+ * +0: Number of variable MTRRs to clear
+ */
+
+ /* Clear all of the variable MTRRs. */
+ popl %ebx
+ movl $MTRRphysBase_MSR(0), %ecx
+ clr %eax
+ clr %edx
+
+1:
+ testl %ebx, %ebx
+ jz 1f
+ wrmsr /* Write MTRR base. */
+ inc %ecx
+ wrmsr /* Write MTRR mask. */
+ inc %ecx
+ dec %ebx
+ jmp 1b
+
+1:
+ /* Get number of MTRRs. */
+ popl %ebx
+ movl $MTRRphysBase_MSR(0), %ecx
+2:
+ testl %ebx, %ebx
+ jz 2f
+
+ /* Low 32 bits of MTRR base. */
+ popl %eax
+ /* Upper 32 bits of MTRR base. */
+ popl %edx
+ /* Write MTRR base. */
+ wrmsr
+ inc %ecx
+ /* Low 32 bits of MTRR mask. */
+ popl %eax
+ /* Upper 32 bits of MTRR mask. */
+ popl %edx
+ /* Write MTRR mask. */
+ wrmsr
+ inc %ecx
+
+ dec %ebx
+ jmp 2b
+2:
+ post_code(0x39)
+
+ /* And enable cache again after setting MTRRs. */
+ movl %cr0, %eax
+ andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
+ movl %eax, %cr0
+
+ post_code(0x3a)
+
+ /* Enable MTRR. */
+ movl $MTRRdefType_MSR, %ecx
+ rdmsr
+ orl $MTRRdefTypeEn, %eax
+ wrmsr
+
+ post_code(0x3b)
+
+ /* Invalidate the cache again. */
+ invd
+
+ post_code(0x3c)
+
+__main:
+ post_code(POST_PREPARE_RAMSTAGE)
+ cld /* Clear direction flag. */
+ call after_cache_as_ram
+
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc
index 2349985..dd45221 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc
@@ -28,10 +28,6 @@
* performs the final stage of initialization.
*/
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/post_code.h>
-#include <cbmem.h>
#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
@@ -125,12 +121,10 @@ CAR_init_done:
* mm1: high 32-bits of TSC value
*/
- /* Create fsp_car_context on stack. */
+ /* Create cache_as_ram_params on stack */
pushl %edx /* bootloader CAR end */
pushl %ecx /* bootloader CAR begin */
pushl %ebp /* FSP_INFO_HEADER */
- /* Create cache_as_ram_params on stack */
- pushl %esp /* chipset_context -> fsp_car_context */
pushl %edi /* bist */
movd %mm1, %eax
pushl %eax /* tsc[63:32] */
@@ -154,122 +148,10 @@ CAR_init_done:
before_romstage:
post_code(0x23)
- /* Call romstage_main(struct cache_as_ram_params *) */
- call romstage_main
-
- /*
- * eax: New stack address
- * ebx: FSP_INFO_HEADER address
- */
-
- /* Switch to the stack in RAM */
- movl %eax, %esp
-
- /* Calculate TempRamExit entry into FSP */
- movl %ebx, %ebp
- mov 0x40(%ebp), %eax
- add 0x1c(%ebp), %eax
-
- /* Build the call frame */
- pushl $0
-
- /* Call TempRamExit */
- call *%eax
- add $4, %esp
- cmp $0, %eax
- jne halt3
-
- /* Display the MTRRs */
- call soc_display_mtrrs
-
- /*
- * The stack contents are initialized in src/soc/intel/common/stack.c
- * to be the following:
- *
- * *
- * *
- * *
- * +36: MTRR mask 1 63:32
- * +32: MTRR mask 1 31:0
- * +28: MTRR base 1 63:32
- * +24: MTRR base 1 31:0
- * +20: MTRR mask 0 63:32
- * +16: MTRR mask 0 31:0
- * +12: MTRR base 0 63:32
- * +8: MTRR base 0 31:0
- * +4: Number of MTRRs to setup (described above)
- * +0: Number of variable MTRRs to clear
- */
-
- /* Clear all of the variable MTRRs. */
- popl %ebx
- movl $MTRRphysBase_MSR(0), %ecx
- clr %eax
- clr %edx
-
-1:
- testl %ebx, %ebx
- jz 1f
- wrmsr /* Write MTRR base. */
- inc %ecx
- wrmsr /* Write MTRR mask. */
- inc %ecx
- dec %ebx
- jmp 1b
-
-1:
- /* Get number of MTRRs. */
- popl %ebx
- movl $MTRRphysBase_MSR(0), %ecx
-2:
- testl %ebx, %ebx
- jz 2f
-
- /* Low 32 bits of MTRR base. */
- popl %eax
- /* Upper 32 bits of MTRR base. */
- popl %edx
- /* Write MTRR base. */
- wrmsr
- inc %ecx
- /* Low 32 bits of MTRR mask. */
- popl %eax
- /* Upper 32 bits of MTRR mask. */
- popl %edx
- /* Write MTRR mask. */
- wrmsr
- inc %ecx
-
- dec %ebx
- jmp 2b
-2:
- post_code(0x39)
-
- /* And enable cache again after setting MTRRs. */
- movl %cr0, %eax
- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
- movl %eax, %cr0
-
- post_code(0x3a)
-
- /* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- orl $MTRRdefTypeEn, %eax
- wrmsr
-
- post_code(0x3b)
-
- /* Invalidate the cache again. */
- invd
-
- post_code(0x3c)
-
-__main:
- post_code(POST_PREPARE_RAMSTAGE)
- cld /* Clear direction flag. */
- call romstage_after_car
+ /* Call cache_as_ram_main(struct cache_as_ram_params *) */
+ call cache_as_ram_main
+#include "after_raminit.S"
movb $0x69, %ah
jmp .Lhlt
@@ -304,17 +186,6 @@ halt2:
movb $0xBB, %ah
jmp .Lhlt
-halt3:
- /*
- * Failures for post code BC - failed in TempRamExit
- *
- * 0x00 - FSP_SUCCESS: Temp RAM Exit completed successfully.
- * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
- * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
- * 0x07 - FSP_DEVICE_ERROR: Temp RAM Exit failed.
- */
- movb $0xBC, %ah
-
.Lhlt:
xchg %al, %ah
#if IS_ENABLED(CONFIG_POST_IO)
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
new file mode 100644
index 0000000..9f87983
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <fsp/car.h>
+#include <soc/intel/common/util.h>
+#include <timestamp.h>
+
+asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
+{
+ /* Initialize timestamp book keeping only once. */
+ timestamp_init(car_params->tsc);
+
+ /* Call into pre-console init code then initialize console. */
+ car_soc_pre_console_init();
+ car_mainboard_pre_console_init();
+ console_init();
+
+ printk(BIOS_DEBUG, "FSP TempRamInit successful\n");
+
+ printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist);
+ printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc);
+
+ if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE ||
+ car_params->bootloader_car_end !=
+ (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) {
+ printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n",
+ CONFIG_DCACHE_RAM_BASE,
+ CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE,
+ (long)car_params->bootloader_car_start,
+ (long)car_params->bootloader_car_end);
+ }
+
+ car_soc_post_console_init();
+ car_mainboard_post_console_init();
+
+ /* Ensure the EC is in the right mode for recovery */
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ google_chromeec_early_init();
+
+ /* Return new stack value in ram back to assembly stub. */
+ return cache_as_ram_stage_main(car_params->fih);
+}
+
+asmlinkage void after_cache_as_ram(void *chipset_context)
+{
+ timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END);
+ printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n");
+ soc_display_mtrrs();
+
+ after_cache_as_ram_stage();
+}
+
+void __attribute__((weak)) car_mainboard_pre_console_init(void)
+{
+}
+
+void __attribute__((weak)) car_soc_pre_console_init(void)
+{
+}
+
+void __attribute__((weak)) car_mainboard_post_console_init(void)
+{
+}
+
+void __attribute__((weak)) car_soc_post_console_init(void)
+{
+}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h
new file mode 100644
index 0000000..8234b37
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/include/fsp/car.h
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef FSP1_1_CAR_H
+#define FSP1_1_CAR_H
+
+#include <arch/cpu.h>
+#include <fsp/api.h>
+#include <stdint.h>
+
+/* cache-as-ram support for FSP 1.1. */
+struct cache_as_ram_params {
+ uint64_t tsc;
+ uint32_t bist;
+ FSP_INFO_HEADER *fih;
+ uintptr_t bootloader_car_start;
+ uintptr_t bootloader_car_end;
+};
+
+/* Entry points from the cache-as-ram assembly code. */
+asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params);
+asmlinkage void after_cache_as_ram(void *chipset_context);
+/* Per stage calls from the above two functions. The void * return from
+ * cache_as_ram_stage_main() is the stack pointer to use in ram after
+ * exiting cache-as-ram mode. */
+void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih);
+void after_cache_as_ram_stage(void);
+
+/* Mainboard and SoC initialization prior to console. */
+void car_mainboard_pre_console_init(void);
+void car_soc_pre_console_init(void);
+/* Mainboard and SoC initialization post console initialization. */
+void car_mainboard_post_console_init(void);
+void car_soc_post_console_init(void);
+
+#endif
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index 0919c66..b3772a2 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -28,13 +28,6 @@
#include <program_loading.h>
#include <commonlib/region.h>
-/* cache-as-ram context for FSP 1.1. */
-struct fsp_car_context {
- FSP_INFO_HEADER *fih;
- uintptr_t bootloader_car_start;
- uintptr_t bootloader_car_end;
-};
-
/* find_fsp() should only be called from assembly code. */
FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
/* Set FSP's runtime information. */
diff --git a/src/mainboard/google/cyan/com_init.c b/src/mainboard/google/cyan/com_init.c
index 00f79dc..e94f585 100644
--- a/src/mainboard/google/cyan/com_init.c
+++ b/src/mainboard/google/cyan/com_init.c
@@ -24,7 +24,7 @@
#include <soc/pci_devs.h>
#include <soc/romstage.h>
-void mainboard_pre_console_init(void)
+void car_mainboard_pre_console_init(void)
{
uint32_t reg;
uint32_t *pad_config_reg;
diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c
index d29eed3..309a73d 100755
--- a/src/mainboard/intel/strago/com_init.c
+++ b/src/mainboard/intel/strago/com_init.c
@@ -33,7 +33,7 @@
/* family number in high byte and inner pad number in lowest byte */
-void mainboard_pre_console_init(void)
+void car_mainboard_pre_console_init(void)
{
uint32_t reg;
uint32_t *pad_config_reg;
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 87b1af0..0b1eab5 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -31,10 +31,6 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci_def.h>
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#endif
#include <elog.h>
#include <romstage_handoff.h>
#include <timestamp.h>
@@ -170,7 +166,7 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps)
}
/* SOC initialization before the console is enabled */
-void soc_pre_console_init(void)
+void car_soc_pre_console_init(void)
{
/* Early chipset initialization */
program_base_addresses();
@@ -178,16 +174,12 @@ void soc_pre_console_init(void)
}
/* SOC initialization after console is enabled */
-void soc_romstage_init(struct romstage_params *params)
+void car_soc_post_console_init(void)
{
/* Continue chipset initialization */
set_max_freq();
spi_init();
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
- /* Ensure the EC is in the right mode for recovery */
- google_chromeec_early_init();
-#endif
lpc_init();
}
diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c
index 932d5c3..0779c55 100644
--- a/src/soc/intel/common/raminit.c
+++ b/src/soc/intel/common/raminit.c
@@ -57,7 +57,6 @@ void raminit(struct romstage_params *params)
unsigned long int data;
EFI_PEI_HOB_POINTERS hob_ptr;
#endif
- struct fsp_car_context *fsp_car_context;
/*
* Find and copy the UPD region to the stack so the platform can modify
@@ -69,8 +68,7 @@ void raminit(struct romstage_params *params)
* region in the FSP binary.
*/
post_code(0x34);
- fsp_car_context = params->chipset_context;
- fsp_header = fsp_car_context->fih;
+ fsp_header = params->chipset_context;
vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset +
fsp_header->ImageBase);
printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr);
diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c
index 42e624c..6fc569c 100644
--- a/src/soc/intel/common/romstage.c
+++ b/src/soc/intel/common/romstage.c
@@ -48,37 +48,22 @@
#include <tpm.h>
#include <vendorcode/google/chromeos/chromeos.h>
-/* Entry from cache-as-ram.inc. */
-asmlinkage void *romstage_main(struct cache_as_ram_params *car_params)
+asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
{
void *top_of_stack;
struct pei_data pei_data;
- struct fsp_car_context *fsp_car_context;
struct romstage_params params = {
- .bist = car_params->bist,
.pei_data = &pei_data,
- .chipset_context = car_params->chipset_context,
+ .chipset_context = fih,
};
- fsp_car_context = car_params->chipset_context;
post_code(0x30);
- /* Save timestamp data */
- timestamp_init(car_params->tsc);
timestamp_add_now(TS_START_ROMSTAGE);
memset(&pei_data, 0, sizeof(pei_data));
- /* Call into pre-console init code. */
- soc_pre_console_init();
- mainboard_pre_console_init();
-
- /* Start console drivers */
- console_init();
-
/* Display parameters */
- printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist);
- printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc);
printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
CONFIG_MMCONF_BASE_ADDRESS);
printk(BIOS_INFO, "Using: %s\n",
@@ -87,25 +72,11 @@ asmlinkage void *romstage_main(struct cache_as_ram_params *car_params)
"No Memory Support"));
/* Display FSP banner */
- printk(BIOS_DEBUG, "FSP TempRamInit successful\n");
- print_fsp_info(fsp_car_context->fih);
-
- if (fsp_car_context->bootloader_car_start != CONFIG_DCACHE_RAM_BASE ||
- fsp_car_context->bootloader_car_end !=
- (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) {
- printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n",
- CONFIG_DCACHE_RAM_BASE,
- CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE,
- (long)fsp_car_context->bootloader_car_start,
- (long)fsp_car_context->bootloader_car_end);
- }
+ print_fsp_info(fih);
/* Get power state */
params.power_state = fill_power_state();
- /* Perform SOC specific initialization. */
- soc_romstage_init(¶ms);
-
/*
* Read and print board version. Done after SOC romstage
* in case PCH needs to be configured to talk to the EC.
@@ -125,6 +96,11 @@ asmlinkage void *romstage_main(struct cache_as_ram_params *car_params)
return top_of_stack;
}
+void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
+{
+ return romstage_main(fih);
+}
+
/* Entry from the mainboard. */
void romstage_common(struct romstage_params *params)
{
@@ -204,13 +180,8 @@ void romstage_common(struct romstage_params *params)
init_tpm(params->power_state->prev_sleep_state == SLEEP_STATE_S3);
}
-asmlinkage void romstage_after_car(void *chipset_context)
+void after_cache_as_ram_stage(void)
{
- timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END);
- printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n");
- soc_after_temp_ram_exit();
- soc_display_mtrrs();
-
/* Load the ramstage. */
copy_and_run();
die("ERROR - Failed to load ramstage!");
@@ -238,11 +209,6 @@ __attribute__((weak)) void mainboard_check_ec_image(
#endif
}
-/* Board initialization before the console is enabled */
-__attribute__((weak)) void mainboard_pre_console_init(void)
-{
-}
-
/* Board initialization before and after RAM is enabled */
__attribute__((weak)) void mainboard_romstage_entry(
struct romstage_params *params)
@@ -443,29 +409,8 @@ __attribute__((weak)) void soc_after_ram_init(struct romstage_params *params)
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
-/* SOC initialization after temporary RAM is disabled */
-__attribute__((weak)) void soc_after_temp_ram_exit(void)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-}
-
-/* SOC initialization before the console is enabled */
-__attribute__((weak)) void soc_pre_console_init(void)
-{
-}
-
/* SOC initialization before RAM is enabled */
__attribute__((weak)) void soc_pre_ram_init(struct romstage_params *params)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
-
-/* SOC initialization after console is enabled */
-__attribute__((weak)) void soc_romstage_init(struct romstage_params *params)
-{
- printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
- /* Ensure the EC is in the right mode for recovery */
- google_chromeec_early_init();
-#endif
-}
diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h
index ac1d6a0..272679f 100644
--- a/src/soc/intel/common/romstage.h
+++ b/src/soc/intel/common/romstage.h
@@ -24,17 +24,12 @@
#include <stdint.h>
#include <arch/cpu.h>
#include <memory_info.h>
+#include <fsp/car.h>
#include <fsp/util.h>
#include <soc/intel/common/util.h>
#include <soc/pei_data.h>
#include <soc/pm.h> /* chip_power_state */
-struct cache_as_ram_params {
- uint64_t tsc;
- uint32_t bist;
- void *chipset_context;
-};
-
struct romstage_params {
unsigned long bist;
struct chipset_power_state *power_state;
@@ -80,7 +75,6 @@ struct romstage_params {
void mainboard_check_ec_image(struct romstage_params *params);
void mainboard_memory_init_params(struct romstage_params *params,
MEMORY_INIT_UPD *memory_params);
-void mainboard_pre_console_init(void);
void mainboard_romstage_entry(struct romstage_params *params);
void mainboard_save_dimm_info(struct romstage_params *params);
void mainboard_add_dimm_info(struct romstage_params *params,
@@ -88,18 +82,14 @@ void mainboard_add_dimm_info(struct romstage_params *params,
int channel, int dimm, int index);
void raminit(struct romstage_params *params);
void report_memory_config(void);
-asmlinkage void romstage_after_car(void *chipset_context);
void romstage_common(struct romstage_params *params);
-asmlinkage void *romstage_main(struct cache_as_ram_params *car_params);
+asmlinkage void *romstage_main(FSP_INFO_HEADER *fih);
void *setup_stack_and_mtrrs(void);
void soc_after_ram_init(struct romstage_params *params);
-void soc_after_temp_ram_exit(void);
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
MEMORY_INIT_UPD *new);
void soc_memory_init_params(struct romstage_params *params,
MEMORY_INIT_UPD *upd);
-void soc_pre_console_init(void);
void soc_pre_ram_init(struct romstage_params *params);
-void soc_romstage_init(struct romstage_params *params);
#endif /* _COMMON_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 9220626..b21eb8a 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -46,8 +46,15 @@
#include <timestamp.h>
#include <vendorcode/google/chromeos/chromeos.h>
-/* SOC initialization before the console is enabled */
-void soc_pre_console_init(void)
+/* SOC initialization before RAM is enabled */
+void soc_pre_ram_init(struct romstage_params *params)
+{
+ /* Prepare to initialize memory */
+ soc_fill_pei_data(params->pei_data);
+}
+
+/* SOC initialization before the console is enabled. */
+void car_soc_pre_console_init(void)
{
/* System Agent Early Initialization */
systemagent_early_init();
@@ -56,14 +63,7 @@ void soc_pre_console_init(void)
pch_uart_init();
}
-/* SOC initialization before RAM is enabled */
-void soc_pre_ram_init(struct romstage_params *params)
-{
- /* Prepare to initialize memory */
- soc_fill_pei_data(params->pei_data);
-}
-
-void soc_romstage_init(struct romstage_params *params)
+void car_soc_post_console_init(void)
{
report_platform_info();
set_max_freq();
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