[coreboot-gerrit] New patch to review for coreboot: intel SOC common: Remove unused parameters

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11814

-gerrit

commit bb6ec60f719cc43aad006a9df32c62b8e21ea670
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Thu Sep 17 12:35:10 2015 -0700

    intel SOC common: Remove unused parameters
    
    Eliminate unused parameters from the console initialization.
    
    BRANCH=none
    BUG=chrome-os-partner:44827
    TEST=Build and run on kunimitsu
    
    Original-Change-Id: Iacacea292d43615e9d2f8e5d3ec67e77f3f08906
    Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/301204
    Original-Commit-Ready: Aaron Durbin <adurbin at chromium.org>
    Original-Tested-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Patrick Georgi <pgeorgi at chromium.org>
    
    Change-Id: I3a0ea948ce106b07cb6aa872375ce588317dc437
    Signed-off-by: Lee Leahy <Leroy.P.Leahy at intel.com>
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/cyan/com_init.c       |  2 +-
 src/mainboard/intel/strago/com_init.c      |  2 +-
 src/soc/intel/braswell/romstage/romstage.c |  2 +-
 src/soc/intel/common/romstage.c            | 10 ++++------
 src/soc/intel/common/romstage.h            |  4 ++--
 src/soc/intel/skylake/romstage/romstage.c  |  2 +-
 6 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/google/cyan/com_init.c b/src/mainboard/google/cyan/com_init.c
index bce0666..00f79dc 100644
--- a/src/mainboard/google/cyan/com_init.c
+++ b/src/mainboard/google/cyan/com_init.c
@@ -24,7 +24,7 @@
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
 
-void mainboard_pre_console_init(struct romstage_params *params)
+void mainboard_pre_console_init(void)
 {
 	uint32_t reg;
 	uint32_t *pad_config_reg;
diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c
index a15d8c3..d29eed3 100755
--- a/src/mainboard/intel/strago/com_init.c
+++ b/src/mainboard/intel/strago/com_init.c
@@ -33,7 +33,7 @@
 
 	/* family number in high byte and inner pad number in lowest byte */
 
-void mainboard_pre_console_init(struct romstage_params *params)
+void mainboard_pre_console_init(void)
 {
 	uint32_t reg;
 	uint32_t *pad_config_reg;
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 2286cd4..00710fe 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -170,7 +170,7 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps)
 }
 
 /* SOC initialization before the console is enabled */
-void soc_pre_console_init(struct romstage_params *params)
+void soc_pre_console_init(void)
 {
 	/* Early chipset initialization */
 	program_base_addresses();
diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c
index f4ee250..e1095b2 100644
--- a/src/soc/intel/common/romstage.c
+++ b/src/soc/intel/common/romstage.c
@@ -70,8 +70,8 @@ asmlinkage void *romstage_main(struct cache_as_ram_params *car_params)
 	memset(&pei_data, 0, sizeof(pei_data));
 
 	/* Call into pre-console init code. */
-	soc_pre_console_init(&params);
-	mainboard_pre_console_init(&params);
+	soc_pre_console_init();
+	mainboard_pre_console_init();
 
 	/* Start console drivers */
 	console_init();
@@ -245,8 +245,7 @@ __attribute__((weak)) void mainboard_check_ec_image(
 }
 
 /* Board initialization before the console is enabled */
-__attribute__((weak)) void mainboard_pre_console_init(
-	struct romstage_params *params)
+__attribute__((weak)) void mainboard_pre_console_init(void)
 {
 }
 
@@ -469,9 +468,8 @@ __attribute__((weak)) void soc_after_temp_ram_exit(void)
 }
 
 /* SOC initialization before the console is enabled */
-__attribute__((weak)) void soc_pre_console_init(struct romstage_params *params)
+__attribute__((weak)) void soc_pre_console_init(void)
 {
-	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
 
 /* SOC initialization before RAM is enabled */
diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h
index 56ab467..c0c7a7b 100644
--- a/src/soc/intel/common/romstage.h
+++ b/src/soc/intel/common/romstage.h
@@ -80,7 +80,7 @@ struct romstage_params {
 void mainboard_check_ec_image(struct romstage_params *params);
 void mainboard_memory_init_params(struct romstage_params *params,
 	MEMORY_INIT_UPD *memory_params);
-void mainboard_pre_console_init(struct romstage_params *params);
+void mainboard_pre_console_init(void);
 void mainboard_romstage_entry(struct romstage_params *params);
 void mainboard_save_dimm_info(struct romstage_params *params);
 void mainboard_add_dimm_info(struct romstage_params *params,
@@ -100,7 +100,7 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
 	MEMORY_INIT_UPD *new);
 void soc_memory_init_params(struct romstage_params *params,
 			    MEMORY_INIT_UPD *upd);
-void soc_pre_console_init(struct romstage_params *params);
+void soc_pre_console_init(void);
 void soc_pre_ram_init(struct romstage_params *params);
 void soc_romstage_init(struct romstage_params *params);
 
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 6804459..0343491 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -47,7 +47,7 @@
 #include <vendorcode/google/chromeos/chromeos.h>
 
 /* SOC initialization before the console is enabled */
-void soc_pre_console_init(struct romstage_params *params)
+void soc_pre_console_init(void)
 {
 	/* System Agent Early Initialization */
 	systemagent_early_init();