[coreboot-gerrit] Patch set updated for coreboot: mainboard: Add support for Advantech SOM-6896
George McCollister (george.mccollister@gmail.com)
gerrit at coreboot.org
Mon Oct 5 21:30:53 CET 2015
George McCollister (george.mccollister at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11802
-gerrit
commit 587334a6f3b3b9b87de306f4bff225846534af12
Author: George McCollister <george.mccollister at gmail.com>
Date: Mon Oct 5 16:09:48 2015 -0500
mainboard: Add support for Advantech SOM-6896
Coreboot files are based on wtm2.
This board is able to boot Linux with working SATA, USB and VGA. I
wasn't able to find a working VGA rom so VGA doesn't work until
booted into Linux. The onboard Ethernet does not currently work, however a
PCIe NIC can be used.
Tested with:
P/N: SOM-6896C7-U2A1E
BLOBs from factory BIOS (descriptor, me, gbe)
BLOBs from yuna (mrc.bin, refcode)
Payload: u-boot (patches coming soon)
Distro: Ubuntu 15.04 installed on a SATA SSD
Kernel: 3.19.0-15-generic
Not tested:
Power management
I2C
SPI
Audio In
HDMI/DP
Change-Id: I3c2cd05de3d9b7585d952464810c7e625641f6c6
Signed-off-by: George McCollister <george.mccollister at gmail.com>
---
src/mainboard/advantech/Kconfig | 16 ++
src/mainboard/advantech/Kconfig.name | 2 +
src/mainboard/advantech/som-6896/Kconfig | 27 ++-
src/mainboard/advantech/som-6896/Kconfig.name | 4 +-
src/mainboard/advantech/som-6896/Makefile.inc | 10 -
src/mainboard/advantech/som-6896/acpi/chromeos.asl | 24 ---
src/mainboard/advantech/som-6896/acpi/ec.asl | 42 +---
.../advantech/som-6896/acpi/mainboard.asl | 4 -
src/mainboard/advantech/som-6896/acpi/platform.asl | 72 -------
src/mainboard/advantech/som-6896/acpi/superio.asl | 4 -
src/mainboard/advantech/som-6896/acpi/thermal.asl | 4 -
src/mainboard/advantech/som-6896/acpi_tables.c | 4 -
src/mainboard/advantech/som-6896/board_info.txt | 7 +-
src/mainboard/advantech/som-6896/chromeos.c | 66 ------
src/mainboard/advantech/som-6896/cmos.layout | 4 -
src/mainboard/advantech/som-6896/devicetree.cb | 40 ++--
src/mainboard/advantech/som-6896/dsdt.asl | 12 +-
src/mainboard/advantech/som-6896/fadt.c | 6 +-
src/mainboard/advantech/som-6896/gpio.h | 8 +-
src/mainboard/advantech/som-6896/graphics.c | 87 --------
src/mainboard/advantech/som-6896/hda_verb.c | 4 -
src/mainboard/advantech/som-6896/i915.c | 232 ---------------------
src/mainboard/advantech/som-6896/intel_dp.c | 167 ---------------
src/mainboard/advantech/som-6896/mainboard.c | 9 +-
src/mainboard/advantech/som-6896/pei_data.c | 10 +-
src/mainboard/advantech/som-6896/romstage.c | 4 -
src/mainboard/advantech/som-6896/thermal.h | 8 +-
27 files changed, 75 insertions(+), 802 deletions(-)
diff --git a/src/mainboard/advantech/Kconfig b/src/mainboard/advantech/Kconfig
new file mode 100644
index 0000000..13051d8
--- /dev/null
+++ b/src/mainboard/advantech/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_ADVANTECH
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/advantech/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/advantech/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string "Mainboard Vendor"
+ default "Advantech"
+
+endif # VENDOR_ADVANTECH
diff --git a/src/mainboard/advantech/Kconfig.name b/src/mainboard/advantech/Kconfig.name
new file mode 100644
index 0000000..8862ffc
--- /dev/null
+++ b/src/mainboard/advantech/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_ADVANTECH
+ bool "Advantech"
diff --git a/src/mainboard/advantech/som-6896/Kconfig b/src/mainboard/advantech/som-6896/Kconfig
index e739efa..a5d3ec1 100644
--- a/src/mainboard/advantech/som-6896/Kconfig
+++ b/src/mainboard/advantech/som-6896/Kconfig
@@ -1,34 +1,27 @@
-if BOARD_INTEL_WTM2
+if BOARD_ADVANTECH_SOM_6896
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SOC_INTEL_BROADWELL
- select BOARD_ROMSIZE_KB_8192
+ select BOARD_ROMSIZE_KB_16384
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
- select MAINBOARD_HAS_CHROMEOS
- select MAINBOARD_HAS_LPC_TPM
- select MAINBOARD_HAS_NATIVE_VGA_INIT
select INTEL_INT15
-config CHROMEOS
- select CHROMEOS_RAMOOPS_DYNAMIC
- select CHROMEOS_VBNV_CMOS
-
config MAINBOARD_DIR
string
- default intel/wtm2
+ default advantech/som-6896
config MAINBOARD_PART_NUMBER
string
- default "WHITETIP MOUNTAIN 2"
+ default "SOM-6896"
config MAX_CPUS
int
- default 16
+ default 8
config VGA_BIOS_FILE
string
@@ -36,10 +29,14 @@ config VGA_BIOS_FILE
config HAVE_IFD_BIN
bool
- default n
+ default y
config HAVE_ME_BIN
bool
- default n
+ default y
+
+config ACPI_BASE_ADDRESS
+ hex
+ default 0x1800
-endif # BOARD_INTEL_WTM2
+endif # BOARD_ADVANTECH_SOM_6896
diff --git a/src/mainboard/advantech/som-6896/Kconfig.name b/src/mainboard/advantech/som-6896/Kconfig.name
index d0a474d..044b184 100644
--- a/src/mainboard/advantech/som-6896/Kconfig.name
+++ b/src/mainboard/advantech/som-6896/Kconfig.name
@@ -1,2 +1,2 @@
-config BOARD_INTEL_WTM2
- bool "Whitetip Mountain 2 CRB"
+config BOARD_ADVANTECH_SOM_6896
+ bool "SOM-6896"
diff --git a/src/mainboard/advantech/som-6896/Makefile.inc b/src/mainboard/advantech/som-6896/Makefile.inc
index 78bd51a..75587aa 100644
--- a/src/mainboard/advantech/som-6896/Makefile.inc
+++ b/src/mainboard/advantech/som-6896/Makefile.inc
@@ -12,16 +12,6 @@
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
-
-romstage-y += chromeos.c
-ramstage-y += chromeos.c
-ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c
-ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += graphics.c
-ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c
romstage-y += pei_data.c
ramstage-y += pei_data.c
diff --git a/src/mainboard/advantech/som-6896/acpi/chromeos.asl b/src/mainboard/advantech/som-6896/acpi/chromeos.asl
deleted file mode 100644
index 9b7727e..0000000
--- a/src/mainboard/advantech/som-6896/acpi/chromeos.asl
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-Name(OIPG, Package() {
- Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // recovery
- Package () { 0x0002, 0, 0xFFFFFFFF, "PCH-LP" }, // developer
- Package () { 0x0003, 0, 0xFFFFFFFF, "PCH-LP" }, // firmware write protect
-})
diff --git a/src/mainboard/advantech/som-6896/acpi/ec.asl b/src/mainboard/advantech/som-6896/acpi/ec.asl
index 9ae5951..acb9ad7 100644
--- a/src/mainboard/advantech/som-6896/acpi/ec.asl
+++ b/src/mainboard/advantech/som-6896/acpi/ec.asl
@@ -1,37 +1,5 @@
-Device (EC0)
-{
- Name (_HID, EISAID ("PNP0C09"))
- Name (_UID, 1)
- Name (_GPE, 10) // GPIO 10 is SMC_RUNTIME_SCI_N
-
- OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
- Field (ERAM, ByteAcc, Lock, Preserve)
- {
- Offset (0x03),
- ACPR, 1, // AC Power (1=present)
- , 2,
- CFAN, 1, // CPU Fan (1=on)
- , 2,
- LIDS, 1, // Lid State (1=open)
- , 1,
- SPTR, 8, // SMBUS Protocol Register
- SSTS, 8, // SMBUS Status Register
- SADR, 8, // SMBUS Address Register
- SCMD, 8, // SMBUS Command Register
- SBFR, 256, // SMBUS Block Buffer
- SCNT, 8, // SMBUS Block Count
-
- Offset (0x3a),
- ECMD, 8, // EC Command Register
-
- Offset (0x82),
- PECL, 8, // PECI fractional (1/64 Celsius)
- PECH, 8, // PECI integer (Celsius)
- }
-
- Name (_CRS, ResourceTemplate()
- {
- IO (Decode16, 0x62, 0x62, 0, 1)
- IO (Decode16, 0x66, 0x66, 0, 1)
- })
-}
+/*
+ * The Advantech som-6896 uses the IT8528e.
+ * If/when enough information is available this file
+ * will be completed.
+ */
diff --git a/src/mainboard/advantech/som-6896/acpi/mainboard.asl b/src/mainboard/advantech/som-6896/acpi/mainboard.asl
index f37b8b7..0140343 100644
--- a/src/mainboard/advantech/som-6896/acpi/mainboard.asl
+++ b/src/mainboard/advantech/som-6896/acpi/mainboard.asl
@@ -12,10 +12,6 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
*/
Device (PWRB)
diff --git a/src/mainboard/advantech/som-6896/acpi/platform.asl b/src/mainboard/advantech/som-6896/acpi/platform.asl
deleted file mode 100644
index 24ddc91..0000000
--- a/src/mainboard/advantech/som-6896/acpi/platform.asl
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* The APM port can be used for generating software SMIs */
-
-OperationRegion (APMP, SystemIO, 0xb2, 2)
-Field (APMP, ByteAcc, NoLock, Preserve)
-{
- APMC, 8, // APM command
- APMS, 8 // APM status
-}
-
-/* Port 80 POST */
-
-OperationRegion (POST, SystemIO, 0x80, 1)
-Field (POST, ByteAcc, Lock, Preserve)
-{
- DBG0, 8
-}
-
-/* SMI I/O Trap */
-Method(TRAP, 1, Serialized)
-{
- Store (Arg0, SMIF) // SMI Function
- Store (0, TRP0) // Generate trap
- Return (SMIF) // Return value of SMI handler
-}
-
-/* The _PIC method is called by the OS to choose between interrupt
- * routing via the i8259 interrupt controller or the APIC.
- *
- * _PIC is called with a parameter of 0 for i8259 configuration and
- * with a parameter of 1 for Local Apic/IOAPIC configuration.
- */
-
-Method(_PIC, 1)
-{
- // Remember the OS' IRQ routing choice.
- Store(Arg0, PICM)
-}
-
-/* The _PTS method (Prepare To Sleep) is called before the OS is
- * entering a sleep state. The sleep state number is passed in Arg0
- */
-
-Method(_PTS,1)
-{
-}
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
- Return(Package(){0,0})
-}
diff --git a/src/mainboard/advantech/som-6896/acpi/superio.asl b/src/mainboard/advantech/som-6896/acpi/superio.asl
index c9c14e4..301fcc7 100644
--- a/src/mainboard/advantech/som-6896/acpi/superio.asl
+++ b/src/mainboard/advantech/som-6896/acpi/superio.asl
@@ -11,10 +11,6 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
*/
/* Values should match those defined in devicetree.cb */
diff --git a/src/mainboard/advantech/som-6896/acpi/thermal.asl b/src/mainboard/advantech/som-6896/acpi/thermal.asl
index 061347c..06a6f00 100644
--- a/src/mainboard/advantech/som-6896/acpi/thermal.asl
+++ b/src/mainboard/advantech/som-6896/acpi/thermal.asl
@@ -11,10 +11,6 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
*/
// Thermal Zone
diff --git a/src/mainboard/advantech/som-6896/acpi_tables.c b/src/mainboard/advantech/som-6896/acpi_tables.c
index a960397..c72fdb8 100644
--- a/src/mainboard/advantech/som-6896/acpi_tables.c
+++ b/src/mainboard/advantech/som-6896/acpi_tables.c
@@ -11,10 +11,6 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
*/
#include <types.h>
diff --git a/src/mainboard/advantech/som-6896/board_info.txt b/src/mainboard/advantech/som-6896/board_info.txt
index 64e00fa..583c34c 100644
--- a/src/mainboard/advantech/som-6896/board_info.txt
+++ b/src/mainboard/advantech/som-6896/board_info.txt
@@ -1,2 +1,5 @@
-Category: eval
-Release year: 2013
+Category: half
+Board name: SOM-6896
+ROM package: SOIC8
+ROM protocol: SPI
+ROM socketed: y
diff --git a/src/mainboard/advantech/som-6896/chromeos.c b/src/mainboard/advantech/som-6896/chromeos.c
deleted file mode 100644
index fe80063..0000000
--- a/src/mainboard/advantech/som-6896/chromeos.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <string.h>
-#include <bootmode.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <soc/gpio.h>
-
-/* Compile-time settings for developer and recovery mode. */
-#define DEV_MODE_SETTING 1
-#define REC_MODE_SETTING 0
-
-#ifndef __PRE_RAM__
-#include <boot/coreboot_tables.h>
-
-#define GPIO_COUNT 6
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- struct lb_gpio *gpio;
-
- gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
- gpios->count = GPIO_COUNT;
-
- gpio = gpios->gpios;
- fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", 0);
- fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", REC_MODE_SETTING);
- fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", DEV_MODE_SETTING);
- fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); // force open
- fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0);
- fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done());
-}
-#endif
-
-int get_developer_mode_switch(void)
-{
- return DEV_MODE_SETTING;
-}
-
-int get_recovery_mode_switch(void)
-{
- return REC_MODE_SETTING;
-}
-
-int get_write_protect_state(void)
-{
- return 0;
-}
diff --git a/src/mainboard/advantech/som-6896/cmos.layout b/src/mainboard/advantech/som-6896/cmos.layout
index 23faeeb..1967717 100644
--- a/src/mainboard/advantech/som-6896/cmos.layout
+++ b/src/mainboard/advantech/som-6896/cmos.layout
@@ -12,10 +12,6 @@
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc.
-##
# -----------------------------------------------------------------
entries
diff --git a/src/mainboard/advantech/som-6896/devicetree.cb b/src/mainboard/advantech/som-6896/devicetree.cb
index 54b2bff..d87c225 100644
--- a/src/mainboard/advantech/som-6896/devicetree.cb
+++ b/src/mainboard/advantech/som-6896/devicetree.cb
@@ -1,22 +1,22 @@
chip soc/intel/broadwell
- # Enable DisplayPort 1 Hotplug with 6ms pulse
- register "gpu_dp_d_hotplug" = "0x06"
+ # Disable digital port d
+ register "gpu_dp_d_hotplug" = "0x00"
- # Enable DisplayPort 0 Hotplug with 6ms pulse
- register "gpu_dp_c_hotplug" = "0x06"
+ # Disable digital port c
+ register "gpu_dp_c_hotplug" = "0x00"
- # Enable DVI Hotplug with 6ms pulse
- register "gpu_dp_b_hotplug" = "0x06"
+ # Disable digital port b
+ register "gpu_dp_b_hotplug" = "0x00"
- register "pirqa_routing" = "0x8b"
- register "pirqb_routing" = "0x8a"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8b"
- register "pirqe_routing" = "0x80"
+ register "pirqa_routing" = "0xa"
+ register "pirqb_routing" = "0xa"
+ register "pirqc_routing" = "0xa"
+ register "pirqd_routing" = "0xa"
+ register "pirqe_routing" = "0xa"
register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x80"
+ register "pirqg_routing" = "0xa"
+ register "pirqh_routing" = "0xa"
register "alt_gp_smi_en" = "0x0000"
register "gpe0_en_1" = "0x00000400"
@@ -24,7 +24,7 @@ chip soc/intel/broadwell
register "gpe0_en_3" = "0x00000000"
register "gpe0_en_4" = "0x00000000"
- register "sata_port_map" = "0x2"
+ register "sata_port_map" = "0x1"
register "sio_acpi_mode" = "1"
device cpu_cluster 0 on
@@ -33,12 +33,12 @@ chip soc/intel/broadwell
device domain 0 on
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
- device pci 03.0 on end # mini-hd audio
+ device pci 03.0 off end # mini-hd audio
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
device pci 15.0 on end # Serial I/O DMA
- device pci 15.1 on end # I2C0
- device pci 15.2 on end # I2C1
+ device pci 15.1 off end # I2C0
+ device pci 15.2 off end # I2C1
device pci 15.3 off end # GSPI0
device pci 15.4 off end # GSPI1
device pci 15.5 off end # UART0
@@ -48,15 +48,15 @@ chip soc/intel/broadwell
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 17.0 off end # SDIO
- device pci 19.0 off end # GbE
+ device pci 19.0 on end # GbE
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 on end # PCIe Port #2
device pci 1c.2 on end # PCIe Port #3
device pci 1c.3 on end # PCIe Port #4
device pci 1c.4 on end # PCIe Port #5
- device pci 1c.5 on end # PCIe Port #6
- device pci 1d.0 off end # USB2 EHCI
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1d.0 on end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on end # LPC bridge
device pci 1f.2 on end # SATA Controller
diff --git a/src/mainboard/advantech/som-6896/dsdt.asl b/src/mainboard/advantech/som-6896/dsdt.asl
index ac12eb7..9e87506 100644
--- a/src/mainboard/advantech/som-6896/dsdt.asl
+++ b/src/mainboard/advantech/som-6896/dsdt.asl
@@ -12,14 +12,8 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
*/
-#define ENABLE_TPM
-
DefinitionBlock(
"dsdt.aml",
"DSDT",
@@ -30,7 +24,7 @@ DefinitionBlock(
)
{
// Some generic macros
- #include "acpi/platform.asl"
+ #include <soc/intel/broadwell/acpi/platform.asl>
// global NVS and variables
#include <soc/intel/broadwell/acpi/globalnvs.asl>
@@ -52,10 +46,6 @@ DefinitionBlock(
// Thermal handler
#include "acpi/thermal.asl"
- // Chrome OS specific
- #include "acpi/chromeos.asl"
- #include <vendorcode/google/chromeos/acpi/chromeos.asl>
-
// Chipset specific sleep states
#include <soc/intel/broadwell/acpi/sleepstates.asl>
diff --git a/src/mainboard/advantech/som-6896/fadt.c b/src/mainboard/advantech/som-6896/fadt.c
index 61e0439..b2d2025 100644
--- a/src/mainboard/advantech/som-6896/fadt.c
+++ b/src/mainboard/advantech/som-6896/fadt.c
@@ -11,16 +11,12 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
*/
#include <string.h>
#include <soc/acpi.h>
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
diff --git a/src/mainboard/advantech/som-6896/gpio.h b/src/mainboard/advantech/som-6896/gpio.h
index 8abb593..99d5acc 100644
--- a/src/mainboard/advantech/som-6896/gpio.h
+++ b/src/mainboard/advantech/som-6896/gpio.h
@@ -11,14 +11,10 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
*/
-#ifndef INTEL_WTM2_GPIO_H
-#define INTEL_WTM2_GPIO_H
+#ifndef ADVANTECH_SOM_6896_GPIO_H
+#define ADVANTECH_SOM_6896_GPIO_H
#include <soc/gpio.h>
diff --git a/src/mainboard/advantech/som-6896/graphics.c b/src/mainboard/advantech/som-6896/graphics.c
deleted file mode 100644
index 64baf18..0000000
--- a/src/mainboard/advantech/som-6896/graphics.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright 2013 Google Inc.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; version 2 of the License.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc.
-*/
-/* this file was for the most part machine generated, and in future
- * will be all machine generated. Avoid editing.
- */
-#include <console/console.h>
-#include <drivers/intel/gma/i915.h>
-
-void graphics_register_reset(u32 aux_ctl, u32 aux_data, int verbose)
-{
-
- io_i915_write32(0x80000000,0x45400);
- io_i915_write32(0x00000000,_CURACNTR);
- io_i915_write32((/* PIPEA */0x0<<24)|0x00000000,_DSPACNTR);
- io_i915_write32(0x00000000,_DSPBCNTR);
- io_i915_write32(0x80000000,CPU_VGACNTRL);
- io_i915_write32(0x00000000,_DSPASIZE+0xc);
- io_i915_write32(0x00000000,_DSPBSURF);
- io_i915_write32(0x00000000,0x4f050);
- io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT |
- DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 |
- DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE |
- DP_SYNC_VS_HIGH |0x00000091,DP_A);
- io_i915_write32(0x00200090,_FDI_RXA_MISC);
- io_i915_write32(0x0a000000,_FDI_RXA_MISC);
- /* not yet documented anywhere that we can find. */
- io_i915_write32(0x00000070,0x46408);
- io_i915_write32(0x04000000,0x42090);
- io_i915_write32(0x40000000,0x4f050);
- io_i915_write32(0x00000000,0x9840);
- io_i915_write32(0xa4000000,0x42090);
- io_i915_write32(0x00004000,0x42080);
- io_i915_write32(0x00ffffff,0x64f80);
- io_i915_write32(0x0007000e,0x64f84);
- io_i915_write32(0x00d75fff,0x64f88);
- io_i915_write32(0x000f000a,0x64f8c);
- io_i915_write32(0x00c30fff,0x64f90);
- io_i915_write32(0x00060006,0x64f94);
- io_i915_write32(0x00aaafff,0x64f98);
- io_i915_write32(0x001e0000,0x64f9c);
- io_i915_write32(0x00ffffff,0x64fa0);
- io_i915_write32(0x000f000a,0x64fa4);
- io_i915_write32(0x00d75fff,0x64fa8);
- io_i915_write32(0x00160004,0x64fac);
- io_i915_write32(0x00c30fff,0x64fb0);
- io_i915_write32(0x001e0000,0x64fb4);
- io_i915_write32(0x00ffffff,0x64fb8);
- io_i915_write32(0x00060006,0x64fbc);
- io_i915_write32(0x00d75fff,0x64fc0);
- io_i915_write32(0x001e0000,0x64fc4);
- io_i915_write32(0x00ffffff,0x64e00);
- io_i915_write32(0x0006000e,0x64e04);
- io_i915_write32(0x00d75fff,0x64e08);
- io_i915_write32(0x0005000a,0x64e0c);
- io_i915_write32(0x00c30fff,0x64e10);
- io_i915_write32(0x00040006,0x64e14);
- io_i915_write32(0x80aaafff,0x64e18);
- io_i915_write32(0x000b0000,0x64e1c);
- io_i915_write32(0x00ffffff,0x64e20);
- io_i915_write32(0x0005000a,0x64e24);
- io_i915_write32(0x00d75fff,0x64e28);
- io_i915_write32(0x000c0004,0x64e2c);
- io_i915_write32(0x80c30fff,0x64e30);
- io_i915_write32(0x000b0000,0x64e34);
- io_i915_write32(0x00ffffff,0x64e38);
- io_i915_write32(0x00040006,0x64e3c);
- io_i915_write32(0x80d75fff,0x64e40);
- io_i915_write32(0x000b0000,0x64e44);
- /* end not yet documented. */
- io_i915_write32(0x10000000,SDEISR+0x30);
-}
diff --git a/src/mainboard/advantech/som-6896/hda_verb.c b/src/mainboard/advantech/som-6896/hda_verb.c
index 1eb70c5..f7b74a1 100644
--- a/src/mainboard/advantech/som-6896/hda_verb.c
+++ b/src/mainboard/advantech/som-6896/hda_verb.c
@@ -11,10 +11,6 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
*/
#include <device/azalia_device.h>
diff --git a/src/mainboard/advantech/som-6896/i915.c b/src/mainboard/advantech/som-6896/i915.c
deleted file mode 100644
index 4a8d25b..0000000
--- a/src/mainboard/advantech/som-6896/i915.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <types.h>
-#include <string.h>
-#include <stdlib.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#include <delay.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <boot/coreboot_tables.h>
-#include <smbios.h>
-#include <device/pci.h>
-#include <ec/google/chromeec/ec.h>
-
-#include <cpu/x86/tsc.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
-#include <edid.h>
-#include <drivers/intel/gma/i915.h>
-
-/* how many bytes do we need for the framebuffer?
- * Well, this gets messy. To get an exact answer, we have
- * to ask the panel, but we'd rather zero the memory
- * and set up the gtt while the panel powers up. So,
- * we take a reasonable guess, secure in the knowledge that the
- * MRC has to overestimate the number of bytes used.
- * 8 MiB is a very safe guess. There may be a better way later, but
- * fact is, the initial framebuffer is only very temporary. And taking
- * a little long is ok; this is done much faster than the AUX
- * channel is ready for IO.
- */
-#define FRAME_BUFFER_BYTES (8*MiB)
-/* how many 4096-byte pages do we need for the framebuffer?
- * There are hard ways to get this, and easy ways:
- * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
- * on this chip (and in fact every Intel graphics chip we've seen).
- */
-#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
-
-static int verbose = 0;
-
-static unsigned int *mmio;
-static unsigned int graphics;
-static unsigned short addrport;
-static unsigned short dataport;
-static unsigned int physbase;
-
-const u32 link_edid_data[] = {
- 0xffffff00, 0x00ffffff, 0x0379e430, 0x00000000,
- 0x04011500, 0x96121ba5, 0xa2d54f02, 0x26935259,
- 0x00545017, 0x01010000, 0x01010101, 0x01010101,
- 0x01010101, 0x6f6d0101, 0xa4a0a000, 0x20306031,
- 0xb510003a, 0x19000010, 0x00000000, 0x00000000,
- 0x00000000, 0x00000000, 0x00000000, 0x4c00fe00,
- 0x69442047, 0x616c7073, 0x20200a79, 0xfe000000,
- 0x31504c00, 0x45513932, 0x50532d31, 0x24003141,
-};
-
-static int ioread = 0, iowrite = 0;
-
-static char *regname(unsigned long addr)
-{
- static char name[16];
- snprintf(name, sizeof (name), "0x%lx", addr);
- return name;
-}
-
-unsigned long io_i915_read32(unsigned long addr)
-{
- unsigned long val;
- outl(addr, addrport);
- val = inl(dataport);
- ioread += 2;
- if (verbose & vio)printk(BIOS_SPEW, "%s: Got %08lx\n", regname(addr), val);
- return val;
-}
-
-void io_i915_write32(unsigned long val, unsigned long addr)
-{
- if (verbose & vio)printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val);
- outl(addr, addrport);
- outl(val, dataport);
- iowrite += 2;
-}
-
-/* GTT is the Global Translation Table for the graphics pipeline.
- * It is used to translate graphics addresses to physical
- * memory addresses. As in the CPU, GTTs map 4K pages.
- * The setgtt function adds a further bit of flexibility:
- * it allows you to set a range (the first two parameters) to point
- * to a physical address (third parameter);the physical address is
- * incremented by a count (fourth parameter) for each GTT in the
- * range.
- * Why do it this way? For ultrafast startup,
- * we can point all the GTT entries to point to one page,
- * and set that page to 0s:
- * memset(physbase, 0, 4096);
- * setgtt(0, 4250, physbase, 0);
- * this takes about 2 ms, and is a win because zeroing
- * the page takes a up to 200 ms.
- * This call sets the GTT to point to a linear range of pages
- * starting at physbase.
- */
-
-static void
-setgtt(int start, int end, unsigned long base, int inc)
-{
- int i;
-
- for(i = start; i < end; i++){
- u32 word = base + i*inc;
- io_i915_write32(word|1,(i*4)|1);
- }
-}
-
-static unsigned long tickspermicrosecond = 1795;
-static unsigned long long globalstart;
-
-static unsigned long
-microseconds(unsigned long long start, unsigned long long end)
-{
- unsigned long ret;
- ret = ((end - start)/tickspermicrosecond);
- return ret;
-}
-
-static unsigned long globalmicroseconds(void)
-{
- return microseconds(globalstart, rdtscll());
-}
-
-static int i915_init_done = 0;
-
-int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
- unsigned int gfx);
-
-int i915lightup(unsigned int pphysbase, unsigned int piobase,
- unsigned int pmmio, unsigned int pgfx)
-{
- int must_cycle_power = 0;
-
- /* frame buffer pointer */
- u32 *l;
- int i;
- unsigned long before_gtt, after_gtt;
-
- mmio = (void *)pmmio;
- addrport = piobase;
- dataport = addrport + 4;
- physbase = pphysbase;
- graphics = pgfx;
- printk(BIOS_SPEW,
- "i915lightup: graphics %p mmio %p"
- "addrport %04x physbase %08x\n",
- (void *)graphics, mmio, addrport, physbase);
- globalstart = rdtscll();
-
- /* turn it on. The VBIOS does it this way, so we hope that's ok. */
- verbose = 0;
- io_i915_write32(0xabcd000f, PCH_PP_CONTROL);
-
- /* the AUX channel needs a small amount of time to spin up.
- * Rather than udelay, do some useful work:
- * Zero out the frame buffer memory,
- * and set the global translation table (GTT)
- */
- printk(BIOS_SPEW, "Set not-White (%08x) for %d pixels\n", 0xffffff,
- FRAME_BUFFER_BYTES/sizeof(u32));
- for(l = (u32 *)graphics, i = 0;
- i < FRAME_BUFFER_BYTES/sizeof(u32); i++){
- l[i] = 0x1122ff;
- }
- printk(BIOS_SPEW, "GTT: set %d pages starting at %p\n",
- FRAME_BUFFER_PAGES, (void *)physbase);
- before_gtt = globalmicroseconds();
- setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
- after_gtt = globalmicroseconds();
-
- /* The reset is basically harmless, and can be
- * repeated by the VBIOS in any event.
- */
-
- graphics_register_reset(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, verbose);
-
- /* failures after this point can return without
- * powering off the panel.
- */
-
- if (1)
- goto fail;
- /* failures after this point MUST power off the panel
- * and wait 600 ms.
- */
-
- i915_init_done = 1;
- return i915_init_done;
-
-fail:
- printk(BIOS_SPEW, "Graphics could not be started;");
- if (must_cycle_power){
- printk(BIOS_SPEW, "Turn off power and wait ...");
- io_i915_write32(0xabcd0000, PCH_PP_CONTROL);
- udelay(600000);
- }
- printk(BIOS_SPEW, "Returning.\n");
- return 0;
-
-}
diff --git a/src/mainboard/advantech/som-6896/intel_dp.c b/src/mainboard/advantech/som-6896/intel_dp.c
deleted file mode 100644
index b389946..0000000
--- a/src/mainboard/advantech/som-6896/intel_dp.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Copyright 2013 Google Inc.
- * Copyright © 2008 Intel Corporation
- *
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Keith Packard <keithp at keithp.com>
- *
- */
-
-#include <console/console.h>
-#include <stdint.h>
-#include <delay.h>
-#include <drivers/intel/gma/i915.h>
-
-u32
-pack_aux(u32 *src32, int src_bytes)
-{
- u8 *src = (u8 *)src32;
- int i;
- u32 v = 0;
-
- if (src_bytes > 4)
- src_bytes = 4;
- for (i = 0; i < src_bytes; i++)
- v |= ((u32) src[i]) << ((3-i) * 8);
- return v;
-}
-
-void
-unpack_aux(u32 src, u8 *dst, int dst_bytes)
-{
-
- int i;
- if (dst_bytes > 4)
- dst_bytes = 4;
- for (i = 0; i < dst_bytes; i++)
- dst[i] = src >> ((3-i) * 8);
-}
-
-int
-intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
- u8 *recv, int recv_size)
-{
- int i;
- int recv_bytes;
- u32 status;
- u32 aux_clock_divider;
- int try, precharge = 5;
-
- /* The clock divider is based off the hrawclk,
- * and would like to run at 2MHz. So, take the
- * hrawclk value and divide by 2 and use that
- *
- * Note that PCH attached eDP panels should use a 125MHz input
- * clock divider.
- */
- /* 200 on link */
- aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
-
- /* Try to wait for any previous AUX channel activity */
- for (try = 0; try < 3; try++) {
- status = io_i915_read32(ch_ctl);
- if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
- break;
- udelay(1000);
- }
-
- if (try == 3) {
- printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
- status = io_i915_read32(ch_ctl);
- printk(BIOS_SPEW, "dp_aux_ch not started status 0x%08x\n",
- status);
- return -1;
- }
-
- /* Must try at least 3 times according to DP spec */
- for (try = 0; try < 5; try++) {
- /* Load the send data into the aux channel data registers */
- for (i = 0; i < send_bytes; i += 4)
- io_i915_write32(send[i], ch_data + i);
-
- /* Send the command and wait for it to complete */
- io_i915_write32(
- DP_AUX_CH_CTL_SEND_BUSY |
- DP_AUX_CH_CTL_TIME_OUT_400us |
- (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
- (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
- (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
- DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
- for (;;) {
- status = io_i915_read32(ch_ctl);
- if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
- break;
- udelay(100);
- }
-
- /* Clear done status and any errors */
- io_i915_write32(
- status |
- DP_AUX_CH_CTL_DONE |
- DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
-
- if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
- DP_AUX_CH_CTL_RECEIVE_ERROR))
- continue;
- if (status & DP_AUX_CH_CTL_DONE)
- break;
- }
-
- if ((status & DP_AUX_CH_CTL_DONE) == 0) {
- printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
- printk(BIOS_SPEW, "dp_aux_ch not done status 0x%08x\n", status);
- return -1;
- }
-
- /* Check for timeout or receive error.
- * Timeouts occur when the sink is not connected
- */
- if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
- printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
- printk(BIOS_SPEW, "dp_aux_ch receive error status 0x%08x\n", status);
- return -1;
- }
-
- /* Timeouts occur when the device isn't connected, so they're
- * "normal" -- don't fill the kernel log with these */
- if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
- printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
- printk(BIOS_SPEW, "dp_aux_ch timeout status 0x%08x\n", status);
- return -1;
- }
-
- /* Unload any bytes sent back from the other side */
- recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
- DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
- if (recv_bytes > recv_size)
- recv_bytes = recv_size;
-
- for (i = 0; i < recv_bytes; i += 4)
- unpack_aux(io_i915_read32(ch_data + i),
- recv + i, recv_bytes - i);
-
- return recv_bytes;
-}
diff --git a/src/mainboard/advantech/som-6896/mainboard.c b/src/mainboard/advantech/som-6896/mainboard.c
index 6027ca7..f5e3eb5 100644
--- a/src/mainboard/advantech/som-6896/mainboard.c
+++ b/src/mainboard/advantech/som-6896/mainboard.c
@@ -12,10 +12,6 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
*/
#include <types.h>
@@ -43,7 +39,10 @@ void mainboard_suspend_resume(void)
static void mainboard_enable(device_t dev)
{
- install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP,
+ GMA_INT15_PANEL_FIT_CENTERING,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT,
+ 0);
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/advantech/som-6896/pei_data.c b/src/mainboard/advantech/som-6896/pei_data.c
index f35ca0e..7408d4b 100644
--- a/src/mainboard/advantech/som-6896/pei_data.c
+++ b/src/mainboard/advantech/som-6896/pei_data.c
@@ -12,10 +12,6 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
*/
#include <stdint.h>
@@ -28,10 +24,10 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
{
/* One installed DIMM per channel */
pei_data->dimm_channel0_disabled = 2;
- pei_data->dimm_channel1_disabled = 2;
+ pei_data->dimm_channel1_disabled = 3;
- pei_data->spd_addresses[0] = 0xa2;
- pei_data->spd_addresses[2] = 0xa2;
+ pei_data->spd_addresses[0] = 0xa0;
+ pei_data->spd_addresses[2] = 0xa0;
pei_data_usb2_port(pei_data, 0, 0x40, 1, USB_OC_PIN_SKIP,
USB_PORT_FRONT_PANEL);
diff --git a/src/mainboard/advantech/som-6896/romstage.c b/src/mainboard/advantech/som-6896/romstage.c
index 4435d64..3c9bb36 100644
--- a/src/mainboard/advantech/som-6896/romstage.c
+++ b/src/mainboard/advantech/som-6896/romstage.c
@@ -12,10 +12,6 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
*/
#include <console/console.h>
diff --git a/src/mainboard/advantech/som-6896/thermal.h b/src/mainboard/advantech/som-6896/thermal.h
index 5863466..cda50df 100644
--- a/src/mainboard/advantech/som-6896/thermal.h
+++ b/src/mainboard/advantech/som-6896/thermal.h
@@ -11,14 +11,10 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
*/
-#ifndef WTM2_THERMAL_H
-#define WTM2_THERMAL_H
+#ifndef ADVANTECH_SOM_6896_THERMAL_H
+#define ADVANTECH_SOM_6896_THERMAL_H
/* Fan is OFF */
#define FAN4_THRESHOLD_OFF 0
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