[coreboot-gerrit] Patch set updated for coreboot: AMD Bettong: add memory configuration for DDR3 and DDR4

[WANG Siyuan (wangsiyuanbuaa@gmail.com)]

WANG Siyuan (wangsiyuanbuaa at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11733

-gerrit

commit 80c2d49a1e001bb1a864e69775d2539ac4a9c8fa
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date:   Fri Jul 3 22:15:31 2015 +0800

    AMD Bettong: add memory configuration for DDR3 and DDR4
    
    1. Bettong Rev A-E are DDR3, Bettong Rev F is DDR4.
    Rev F's SPD address is different from DDR3.
    
                0   1
    Channel A  A0  A2
    Channel B  A4  AC
    
    2. DDR4 uses different memory configuration in AGESA.
    Pass memory configuration parameters in agesawrapper_amdinitpost.
    
    3. Tested on Rev C and Rev F.
    Both of them can boot to Windows 8 and have the correct memory size.
    
    Change-Id: Ia0d35ebf1b65c399abc3777ee6bdb107437a4345
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
    Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
---
 src/northbridge/amd/pi/00660F01/dimmSpd.c | 26 +++++++++++++++++------
 src/northbridge/amd/pi/agesawrapper.c     | 34 +++++++++++++++++++++++++++++++
 2 files changed, 54 insertions(+), 6 deletions(-)

diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c
index 6996f83..7e441bb 100644
--- a/src/northbridge/amd/pi/00660F01/dimmSpd.c
+++ b/src/northbridge/amd/pi/00660F01/dimmSpd.c
@@ -20,6 +20,7 @@
 #include <device/pci_def.h>
 #include <device/device.h>
 #include <stdlib.h>
+#include <string.h>
 
 /* warning: Porting.h includes an open #pragma pack(1) */
 #include "Porting.h"
@@ -27,22 +28,35 @@
 #include "amdlib.h"
 #include "chip.h"
 #include "northbridge/amd/pi/dimmSpd.h"
+#if IS_ENABLED(CONFIG_BOARD_AMD_BETTONG)
+#include <boardid.h>
+#endif
 
 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
 {
 	int spdAddress;
 	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
-	ROMSTAGE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
+	struct northbridge_amd_pi_00660F01_config config;
+	memcpy(&config, dev->chip_info, sizeof(config));
 
-	if ((dev == 0) || (config == 0))
+#if IS_ENABLED(CONFIG_BOARD_AMD_BETTONG)
+	if (board_id() == 'F') {
+		config.spdAddrLookup[0][0][0] = 0xA0;
+		config.spdAddrLookup[0][0][1] = 0xA2;
+		config.spdAddrLookup[0][1][0] = 0xA4;
+		config.spdAddrLookup[0][1][1] = 0xAC;
+	}
+#endif
+
+	if (dev == 0)
 		return AGESA_ERROR;
-	if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup))
+	if (info->SocketId >= ARRAY_SIZE(config.spdAddrLookup))
 		return AGESA_ERROR;
-	if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0]))
+	if (info->MemChannelId >= ARRAY_SIZE(config.spdAddrLookup[0]))
 		return AGESA_ERROR;
-	if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0]))
+	if (info->DimmId >= ARRAY_SIZE(config.spdAddrLookup[0][0]))
 		return AGESA_ERROR;
-	spdAddress = config->spdAddrLookup
+	spdAddress = config.spdAddrLookup
 		[info->SocketId] [info->MemChannelId] [info->DimmId];
 	if (spdAddress == 0)
 		return AGESA_ERROR;
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c
index 9bdf340..778b0db 100644
--- a/src/northbridge/amd/pi/agesawrapper.c
+++ b/src/northbridge/amd/pi/agesawrapper.c
@@ -26,6 +26,10 @@
 #include <heapManager.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/BiosCallOuts.h>
+#include <PlatformMemoryConfiguration.h>
+#if IS_ENABLED(CONFIG_BOARD_AMD_BETTONG)
+#include <boardid.h>
+#endif
 
 VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
 VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
@@ -136,6 +140,36 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
 	AmdCreateStruct (&AmdParamStruct);
 	PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
 
+	PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
+		DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
+		NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+		NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+		MOTHER_BOARD_LAYERS (LAYERS_6),
+		MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+		CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+		ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+		CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+		PSO_END
+	};
+
+	PSO_ENTRY DDR3PlatformMemoryConfiguration[] = {
+		DRAM_TECHNOLOGY(ANY_SOCKET, DDR3_TECHNOLOGY),
+		NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+		NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+		MOTHER_BOARD_LAYERS (LAYERS_6),
+		MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+		CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+		ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+		CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+		PSO_END
+	};
+
+#if IS_ENABLED(CONFIG_BOARD_AMD_BETTONG)
+	if (board_id() == 'F')
+		PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
+	else
+		PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR3PlatformMemoryConfiguration;
+#endif
 	// Do not use IS_ENABLED here.  CONFIG_GFXUMA should always have a value.  Allow
 	// the compiler to flag the error if CONFIG_GFXUMA is not set.
 	PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE;