[coreboot-gerrit] Patch set updated for coreboot: AMD Bettong: add FCH's GPIO, UART and I2C support

[WANG Siyuan (wangsiyuanbuaa@gmail.com)]

WANG Siyuan (wangsiyuanbuaa at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11750

-gerrit

commit 2f0820b9b1feb9374a2d2d6134531da7ebd28d0b
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date:   Wed Sep 30 04:51:28 2015 +0800

    AMD Bettong: add FCH's GPIO, UART and I2C support
    
    Merlin Falcon's FCH has GPIO, UART and I2C. All of them are controlled
    by registers mapped at MMIO space.
    This ASL code is used for Windows drivers.
    
    TEST:
    1. Boot Windows 8 or Windows 10.
    2. Install AMD Catalyst driver.
    3. AMD FPIO, UART and I2C can be found in device manager.
    4. I2C passed Multi Interface Test Tool (MITT) test.
    
    Change-Id: I7ffe3fe0046d9a078cc38176c29a8e334646a5a3
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
    Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
---
 src/mainboard/amd/bettong/dsdt.asl                 |   1 +
 src/southbridge/amd/pi/hudson/acpi/carrizo_fch.asl | 101 +++++++++++++++++++++
 2 files changed, 102 insertions(+)

diff --git a/src/mainboard/amd/bettong/dsdt.asl b/src/mainboard/amd/bettong/dsdt.asl
index 5e0febb..12b04cd 100644
--- a/src/mainboard/amd/bettong/dsdt.asl
+++ b/src/mainboard/amd/bettong/dsdt.asl
@@ -72,6 +72,7 @@ DefinitionBlock (
 
 		/* Describe PCI INT[A-H] for the Southbridge */
 		#include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
+		#include <southbridge/amd/pi/hudson/acpi/carrizo_fch.asl>
 
 	} /* End \_SB scope */
 
diff --git a/src/southbridge/amd/pi/hudson/acpi/carrizo_fch.asl b/src/southbridge/amd/pi/hudson/acpi/carrizo_fch.asl
new file mode 100644
index 0000000..5bfb366
--- /dev/null
+++ b/src/southbridge/amd/pi/hudson/acpi/carrizo_fch.asl
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+Device(GPIO) {
+	Name (_HID, "AMD0030")
+	Name (_CID, "AMD0030")
+	Name(_UID, 0)
+
+	Method (_CRS, 0x0, NotSerialized) {
+		Name (RBUF, ResourceTemplate () {
+			//
+			// Interrupt resource. In this example, banks 0 & 1 share the same
+			// interrupt to the parent controller and similarly banks 2 & 3.
+			//
+			// N.B. The definition below is chosen for an arbitrary
+			//      test platform. It needs to be changed to reflect the hardware
+			//      configuration of the actual platform
+			//
+			Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
+
+			//
+			// Memory resource. The definition below is chosen for an arbitrary
+			// test platform. It needs to be changed to reflect the hardware
+			// configuration of the actual platform.
+			//
+			Memory32Fixed(ReadWrite, 0xFED81500, 0x300)
+		})
+
+		Return (RBUF)
+	}
+
+	Method (_STA, 0x0, NotSerialized) {
+			Return (0x0F)
+	}
+}
+
+Device(FUR0) {
+	Name(_HID,"AMD0020")
+	Name(_UID,0x0)
+	Name(_CRS, ResourceTemplate() {
+		IRQ(Edge, ActiveHigh, Exclusive) {10}
+		Memory32Fixed(ReadWrite, 0xFEDC6000, 0x2000)
+	})
+	Method (_STA, 0x0, NotSerialized) {
+		Return (0x0F)
+	}
+}
+
+Device(FUR1) {
+	Name(_HID,"AMD0020")
+	Name(_UID,0x1)
+	Name(_CRS, ResourceTemplate() {
+			IRQ(Edge, ActiveHigh, Exclusive) {11}
+			Memory32Fixed(ReadWrite, 0xFEDC8000, 0x2000)
+	})
+	Method (_STA, 0x0, NotSerialized) {
+			Return (0x0F)
+	}
+}
+
+Device(I2CA) {
+	Name(_HID,"AMD0010")
+	Name(_UID,0x0)
+	Name(_CRS, ResourceTemplate() {
+		IRQ(Edge, ActiveHigh, Exclusive) {3}
+		Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000)
+	})
+
+	Method (_STA, 0x0, NotSerialized) {
+		Return (0x0F)
+	}
+}
+
+Device(I2CB)
+{
+	Name(_HID,"AMD0010")
+	Name(_UID,0x1)
+	Name(_CRS, ResourceTemplate() {
+		IRQ(Edge, ActiveHigh, Exclusive) {15}
+		Memory32Fixed(ReadWrite, 0xFEDC3000, 0x1000)
+	})
+	Method (_STA, 0x0, NotSerialized) {
+		Return (0x0F)
+	}
+}