[coreboot-gerrit] Patch set updated for coreboot: northbridge/intel/sandybridge: Fix random raminit failures

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11248

-gerrit

commit 2e092a39b94470337fdf1886d6b5833577653277
Author: Patrick Rudolph <siro at das-labor.org>
Date:   Mon Aug 17 19:24:12 2015 +0200

    northbridge/intel/sandybridge: Fix random raminit failures
    
    Issue observed:
        Intel raminit works in about 50% of all test-cases on lenovo x220.
    
    Problem solution:
        Prefer a smaller valid value over the measured one for
        initial timB timings.
    
    Final testing result:
        Tests on x220 shows that the issue was resolved.
        The test system booted successfully ten times in a row.
        Tests on Gigabyte GA-B75M-D3H revealed no regressions.
    
    Test system:
        * Intel Pentium CPU G2130
        * Gigabyte GA-B75M-D3H
        * DIMM: "Crucial 2GB 256Mx64 CT2566aBA160BJ"
    
    Change-Id: I1a115a45d5febf351d89721ece79eaf43f7ee8a0
    Signed-off-by: Patrick Rudolph <siro at das-labor.org>
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/northbridge/intel/sandybridge/raminit.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 76f62a6..f732b6e 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -2266,7 +2266,17 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank)
 	}
 	FOR_ALL_LANES {
 		struct run rn = get_longest_zero_run(statistics[lane], 128);
-		ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start;
+		if (rn.start < rn.middle) {
+			ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start;
+		} else {
+			/* In this case statistics[lane][7f] and statistics[lane][0] are
+			 * both zero.
+			 * Prefer a smaller value over rn.start to prevent failures in
+			 * the following write tests.
+			 */
+			ctrl->timings[channel][slotrank].lanes[lane].timB = 0;
+		}
+
 		if (rn.all)
 			die("timB discovery failed");
 		printram("Bval: %d, %d, %d, %x\n", channel, slotrank,