[coreboot-gerrit] New patch to review for coreboot: vboot: provide CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL option
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Thu Oct 1 22:58:44 CET 2015
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11777
-gerrit
commit 6c3cbff6cecd8594581662fe442a735b7a9c1612
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Oct 1 16:27:55 2015 -0500
vboot: provide CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL option
Certain chipsets provide their own main symbol for verstage.
Therefore, it's necessary to know this so that those chipsets
can leverage the common verstage flow.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built nyan using this option.
Change-Id: If80784aa47b27f0ad286babcf0f42ce198b929e9
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/vendorcode/google/chromeos/vboot2/Kconfig | 7 +++++++
src/vendorcode/google/chromeos/vboot2/verstage.c | 2 ++
2 files changed, 9 insertions(+)
diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig
index c5c46e5..33c33a5 100644
--- a/src/vendorcode/google/chromeos/vboot2/Kconfig
+++ b/src/vendorcode/google/chromeos/vboot2/Kconfig
@@ -65,6 +65,13 @@ config RETURN_FROM_VERSTAGE
reused by the succeeding stage. This is useful if a ram space is too
small to fit both the verstage and the succeeding stage.
+config CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL
+ bool "The chipset provides the main() entry point for verstage"
+ default n
+ depends on SEPARATE_VERSTAGE
+ help
+ The chipset code provides their own main() entry point.
+
# These VBOOT_X_INDEX are the position of X in FW_MAIN_A/B region. The index
# table is created by cros_bundle_firmware at build time based on the positions
# of the blobs listed in fmap.dts and stored at the top of FW_MAIN_A/B region.
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.c b/src/vendorcode/google/chromeos/vboot2/verstage.c
index 9556359..751f588 100644
--- a/src/vendorcode/google/chromeos/vboot2/verstage.c
+++ b/src/vendorcode/google/chromeos/vboot2/verstage.c
@@ -42,5 +42,7 @@ void verstage(void)
}
}
+#if !IS_ENABLED(CONFIG_CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL)
/* This is for boards that rely on main() for an entry point of a stage. */
void main(void) __attribute__((alias ("verstage")));
+#endif
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