[coreboot-gerrit] New patch to review for coreboot: lenovo/t420: Add new port - NOT FOR MERGE
Nicolas Reinecke (nr@das-labor.org)
gerrit at coreboot.org
Thu Oct 1 13:41:28 CET 2015
Nicolas Reinecke (nr at das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11765
-gerrit
commit 2f225b990e8655ffd94e39c40296de497cd2bb7f
Author: Nicolas Reinecke <nr at das-labor.org>
Date: Thu Oct 1 15:34:37 2015 +0200
lenovo/t420: Add new port - NOT FOR MERGE
This is based on t420s. Not tested.
There is no support for nvidia gpu and optimus.
Signed-off-by: Nicolas Reinecke <nr at das-labor.org>
Change-Id: Ie9405966e56180ac1c43a3c5b83181ee500177c8
---
src/mainboard/lenovo/t420/Kconfig | 78 ++++++++
src/mainboard/lenovo/t420/Kconfig.name | 2 +
src/mainboard/lenovo/t420/Makefile.inc | 21 ++
src/mainboard/lenovo/t420/acpi/ec.asl | 25 +++
src/mainboard/lenovo/t420/acpi/platform.asl | 39 ++++
src/mainboard/lenovo/t420/acpi/superio.asl | 1 +
src/mainboard/lenovo/t420/acpi_tables.c | 44 +++++
src/mainboard/lenovo/t420/board_info.txt | 6 +
src/mainboard/lenovo/t420/cmos.default | 17 ++
src/mainboard/lenovo/t420/cmos.layout | 145 ++++++++++++++
src/mainboard/lenovo/t420/devicetree.cb | 182 +++++++++++++++++
src/mainboard/lenovo/t420/dsdt.asl | 67 +++++++
src/mainboard/lenovo/t420/gpio.c | 290 ++++++++++++++++++++++++++++
src/mainboard/lenovo/t420/hda_verb.c | 73 +++++++
src/mainboard/lenovo/t420/mainboard.c | 59 ++++++
src/mainboard/lenovo/t420/romstage.c | 73 +++++++
src/mainboard/lenovo/t420/smihandler.c | 146 ++++++++++++++
src/mainboard/lenovo/t420/thermal.h | 30 +++
18 files changed, 1298 insertions(+)
diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig
new file mode 100644
index 0000000..3cc3c44
--- /dev/null
+++ b/src/mainboard/lenovo/t420/Kconfig
@@ -0,0 +1,78 @@
+if BOARD_LENOVO_T420
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select SYSTEM_TYPE_LAPTOP
+ select CPU_INTEL_SOCKET_RPGA988B
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
+ select SOUTHBRIDGE_INTEL_BD82X6X
+ select EC_LENOVO_PMH7
+ select EC_LENOVO_H8
+ select NO_UART_ON_SUPERIO
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select HAVE_ACPI_RESUME
+ select INTEL_INT15
+ select VGA
+ select INTEL_EDID
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
+ select SANDYBRIDGE_LVDS
+ select ENABLE_VMX
+ select DRIVERS_RICOH_RCE822
+ select MAINBOARD_HAS_LPC_TPM
+
+ # Workaround for EC/KBC IRQ1.
+ select SERIRQ_CONTINUOUS_MODE
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+config MAINBOARD_DIR
+ string
+ default lenovo/t420
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "ThinkPad T420"
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX
+ int
+ default 2
+
+config DRAM_RESET_GATE_GPIO
+ int
+ default 10
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0126.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0126"
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x17aa
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x21ce
+
+endif # BOARD_LENOVO_T420
diff --git a/src/mainboard/lenovo/t420/Kconfig.name b/src/mainboard/lenovo/t420/Kconfig.name
new file mode 100644
index 0000000..75570ad
--- /dev/null
+++ b/src/mainboard/lenovo/t420/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_LENOVO_T420
+ bool "ThinkPad T420"
diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc
new file mode 100644
index 0000000..b0743b5
--- /dev/null
+++ b/src/mainboard/lenovo/t420/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+romstage-y += gpio.c
diff --git a/src/mainboard/lenovo/t420/acpi/ec.asl b/src/mainboard/lenovo/t420/acpi/ec.asl
new file mode 100644
index 0000000..1bacbba
--- /dev/null
+++ b/src/mainboard/lenovo/t420/acpi/ec.asl
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <ec/lenovo/h8/acpi/ec.asl>
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+}
diff --git a/src/mainboard/lenovo/t420/acpi/platform.asl b/src/mainboard/lenovo/t420/acpi/platform.asl
new file mode 100644
index 0000000..232f7d9
--- /dev/null
+++ b/src/mainboard/lenovo/t420/acpi/platform.asl
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+ \_SB.PCI0.LPCB.EC.RADI(0)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ /* ME may not be up yet. */
+ Store (0, \_TZ.MEB1)
+ Store (0, \_TZ.MEB2)
+
+ /* Not implemented. */
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/lenovo/t420/acpi/superio.asl b/src/mainboard/lenovo/t420/acpi/superio.asl
new file mode 100644
index 0000000..03b65bc
--- /dev/null
+++ b/src/mainboard/lenovo/t420/acpi/superio.asl
@@ -0,0 +1 @@
+#include <drivers/pc80/ps2_controller.asl>
diff --git a/src/mainboard/lenovo/t420/acpi_tables.c b/src/mainboard/lenovo/t420/acpi_tables.c
new file mode 100644
index 0000000..041e4e3
--- /dev/null
+++ b/src/mainboard/lenovo/t420/acpi_tables.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/acpigen.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include "thermal.h"
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+}
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ acpi_update_thermal_table(gnvs);
+}
diff --git a/src/mainboard/lenovo/t420/board_info.txt b/src/mainboard/lenovo/t420/board_info.txt
new file mode 100644
index 0000000..f27808b
--- /dev/null
+++ b/src/mainboard/lenovo/t420/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8 / WSON-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
+Release year: 2010
diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
new file mode 100644
index 0000000..cf01726
--- /dev/null
+++ b/src/mainboard/lenovo/t420/cmos.default
@@ -0,0 +1,17 @@
+boot_option=Fallback
+last_boot=Fallback
+baud_rate=115200
+debug_level=Spew
+power_on_after_fail=Enable
+nmi=Enable
+volume=0x3
+first_battery=Primary
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+touchpad=Enable
+sata_mode=AHCI
+fn_ctrl_swap=Disable
+sticky_fn=Disable
+trackpoint=Enable
+hyper_threading=Enable
\ No newline at end of file
diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout
new file mode 100644
index 0000000..77c0a11
--- /dev/null
+++ b/src/mainboard/lenovo/t420/cmos.layout
@@ -0,0 +1,145 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+400 8 h 0 volume
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+
+# coreboot config options: EC
+411 1 e 8 first_battery
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 touchpad
+415 1 e 1 wlan
+416 1 e 1 trackpoint
+417 1 e 1 fn_ctrl_swap
+418 1 e 1 sticky_fn
+419 1 e 1 power_management_beeps
+421 1 e 9 sata_mode
+#422 2 r 1 unused
+
+# coreboot config options: cpu
+424 1 e 2 hyper_threading
+#425 7 r 0 unused
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+#435 549 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+8 0 Secondary
+8 1 Primary
+9 0 AHCI
+9 1 Compatible
+10 0 Both
+10 1 Keyboard only
+10 2 Thinklight only
+10 3 None
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb
new file mode 100644
index 0000000..c519a29
--- /dev/null
+++ b/src/mainboard/lenovo/t420/devicetree.cb
@@ -0,0 +1,182 @@
+chip northbridge/intel/sandybridge
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+
+ # Enable DisplayPort Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+ # Enable Panel as LVDS and configure power delays
+ register "gpu_panel_port_select" = "0" # LVDS
+ register "gpu_panel_power_cycle_delay" = "1"
+ register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms
+ register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms
+ register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
+ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gfx.lvds_dual_channel" = "1"
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gfx.lvds_num_lanes" = "4"
+ register "gpu_cpu_backlight" = "0x1155"
+ register "gpu_pch_backlight" = "0x06100610"
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_rPGA988B
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
+
+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
+ end
+ end
+
+ device domain 0 on
+ device pci 00.0 on
+ subsystemid 0x17aa 0x21ce
+ end # host bridge
+ device pci 01.0 off end # PCIe Bridge for discrete graphics
+ device pci 02.0 on
+ subsystemid 0x17aa 0x21ce
+ end # Integrated Graphics Controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "alt_gp_smi_en" = "0x0000"
+ register "gpi1_routing" = "2"
+ register "gpi13_routing" = "2"
+
+ # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock) & 5 (eSATA)
+ register "sata_port_map" = "0x37"
+ # Set max SATA speed to 6.0 Gb/s
+ register "sata_interface_speed_support" = "0x3"
+
+ register "gen1_dec" = "0x7c1601"
+ register "gen2_dec" = "0x0c15e1"
+ register "gen4_dec" = "0x0c06a1"
+
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
+
+ # Enable zero-based linear PCIe root port functions
+ register "pcie_port_coalesce" = "1"
+
+ register "c2_latency" = "101" # c2 not supported
+ register "p_cnt_throttling_supported" = "1"
+
+ device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 on
+ subsystemid 0x17aa 0x21ce
+ end # Intel Gigabit Ethernet
+ device pci 1a.0 on
+ subsystemid 0x17aa 0x21ce
+ end # USB Enhanced Host Controller #2
+ device pci 1b.0 on
+ subsystemid 0x17aa 0x21ce
+ end # High Definition Audio Controller
+ device pci 1c.0 off end # PCIe Port #1
+ device pci 1c.1 on
+ subsystemid 0x17aa 0x21ce
+ end # PCIe Port #2 Integrated Wireless LAN
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 on
+ subsystemid 0x17aa 0x21ce
+ end # PCIe Port #4 ExpressCard
+ device pci 1c.4 on
+ subsystemid 0x17aa 0x21ce
+ chip drivers/ricoh/rce822
+ register "sdwppol" = "1"
+ register "disable_mask" = "0x87"
+ device pci 00.0 on
+ subsystemid 0x17aa 0x21ce
+ end
+ end
+ end # PCIe Port #5 (Ricoh SD & FW)
+ device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe)
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on
+ subsystemid 0x17aa 0x21ce
+ end # USB Enhanced Host Controller #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on
+ subsystemid 0x17aa 0x21ce
+ chip ec/lenovo/pmh7
+ device pnp ff.1 on # dummy
+ end
+ register "backlight_enable" = "0x01"
+ register "dock_event_enable" = "0x01"
+ end
+
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+
+ chip ec/lenovo/h8
+ device pnp ff.2 on # dummy
+ io 0x60 = 0x62
+ io 0x62 = 0x66
+ io 0x64 = 0x1600
+ io 0x66 = 0x1604
+ end
+
+ register "config0" = "0xa7"
+ register "config1" = "0x01"
+ register "config2" = "0xa0"
+ register "config3" = "0xe2"
+
+ register "has_keyboard_backlight" = "0"
+
+ register "beepmask0" = "0x02"
+ register "beepmask1" = "0x86"
+ register "has_power_management_beeps" = "1"
+ register "event2_enable" = "0xff"
+ register "event3_enable" = "0xff"
+ register "event4_enable" = "0xf0"
+ register "event5_enable" = "0x3c"
+ register "event6_enable" = "0x00"
+ register "event7_enable" = "0xa1"
+ register "event8_enable" = "0x7b"
+ register "event9_enable" = "0xff"
+ register "eventa_enable" = "0x00"
+ register "eventb_enable" = "0x00"
+ register "eventc_enable" = "0xff"
+ register "eventd_enable" = "0xff"
+ register "evente_enable" = "0x0d"
+ end
+ end # LPC Controller
+ device pci 1f.2 on
+ subsystemid 0x17aa 0x21ce
+ end # 6 port SATA AHCI Controller
+ device pci 1f.3 on
+ subsystemid 0x17aa 0x21ce
+ # eeprom, 8 virtual devices, same chip
+ chip drivers/i2c/at24rf08c
+ device i2c 54 on end
+ device i2c 55 on end
+ device i2c 56 on end
+ device i2c 57 on end
+ device i2c 5c on end
+ device i2c 5d on end
+ device i2c 5e on end
+ device i2c 5f on end
+ end
+ end # SMBus Controller
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 on
+ subsystemid 0x17aa 0x21ce
+ end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl
new file mode 100644
index 0000000..64e4e9f
--- /dev/null
+++ b/src/mainboard/lenovo/t420/dsdt.asl
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#define THINKPAD_EC_GPE 17
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+#define EC_LENOVO_H8_ME_WORKAROUND 1
+#define HAVE_LCD_SCREEN 1
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+ }
+ }
+
+ /*
+ * LPC Trusted Platform Module
+ */
+ Scope (\_SB.PCI0.LPCB)
+ {
+ #include <drivers/pc80/tpm/acpi/tpm.asl>
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/lenovo/t420/gpio.c b/src/mainboard/lenovo/t420/gpio.c
new file mode 100644
index 0000000..af52a38
--- /dev/null
+++ b/src/mainboard/lenovo/t420/gpio.c
@@ -0,0 +1,290 @@
+#include "southbridge/intel/bd82x6x/gpio.h"
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO, // -USB30_SMIB - input
+ .gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input
+ .gpio2 = GPIO_MODE_GPIO, // -LCD_PRESENCE - input
+ .gpio3 = GPIO_MODE_GPIO, // DOCKID0 - input
+ .gpio4 = GPIO_MODE_GPIO, // DOCKID1 - input
+ .gpio5 = GPIO_MODE_GPIO, // DOCKID2 - input
+ .gpio6 = GPIO_MODE_GPIO, // SYSTEM_DP_HPD - input
+ .gpio7 = GPIO_MODE_GPIO, // pullup
+ .gpio8 = GPIO_MODE_GPIO, // pulldown - INTEGRATED ENABLED(FCIM) 0 / DISABLED (BTM) 1
+ .gpio9 = GPIO_MODE_NATIVE, // OC5 - -USB_PORT9_OC5 - input
+ .gpio10 = GPIO_MODE_GPIO, // DRAMRST_GATE_ON - output
+ .gpio11 = GPIO_MODE_NATIVE, // SMBALERT# pullup
+ .gpio12 = GPIO_MODE_NATIVE, // LANPHYPC - output
+ .gpio13 = GPIO_MODE_GPIO, // -EC_WAKE - input
+ .gpio14 = GPIO_MODE_NATIVE, // OC7 - pullup
+ .gpio15 = GPIO_MODE_GPIO, // pullup - ME CRYPTO STRAP WITH TLS CONFIDENTIALITY
+ .gpio16 = GPIO_MODE_NATIVE, // SATA4GP - SATA_DOCK_DTCT - input from gpio33
+ .gpio17 = GPIO_MODE_GPIO, // DGFX_PW RGD - input
+ .gpio18 = GPIO_MODE_NATIVE, // PCIECLKRQ1 - -CLKREQ_WLAN - input
+ .gpio19 = GPIO_MODE_NATIVE, // SATA1GP - SATA_BAY_DTCT - input to gpio22
+ .gpio20 = GPIO_MODE_NATIVE, // PCIECLKRQ2 - pullup
+ .gpio21 = GPIO_MODE_GPIO, // -DISCRETE_GFX_PRESENCE - input
+ .gpio22 = GPIO_MODE_GPIO, // SATA_BAY_DTCT - output to SATA1GP
+ .gpio23 = GPIO_MODE_NATIVE, // LDRQ1 - TP84
+ .gpio24 = GPIO_MODE_GPIO, // pullup
+ .gpio25 = GPIO_MODE_NATIVE, // PCIECLKRQ3 - -CLKREQ_EXC - input
+ .gpio26 = GPIO_MODE_NATIVE, // PCIECLKRQ4 - pullup
+ .gpio27 = GPIO_MODE_GPIO, // -MSATA_DTCT - input
+ .gpio28 = GPIO_MODE_GPIO, // pulldown possible
+ .gpio29 = GPIO_MODE_GPIO, // SLP_LAN - -PCH_SLP_LAN
+ .gpio30 = GPIO_MODE_NATIVE, // SUSPWRDNACK - output
+ .gpio31 = GPIO_MODE_NATIVE, // ACPRESENT - input
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_OUTPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio18 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_INPUT,
+ .gpio26 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+ .gpio30 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_HIGH,
+ .gpio1 = GPIO_LEVEL_HIGH,
+ .gpio2 = GPIO_LEVEL_LOW,
+ .gpio3 = GPIO_LEVEL_HIGH,
+ .gpio4 = GPIO_LEVEL_HIGH,
+ .gpio5 = GPIO_LEVEL_HIGH,
+ .gpio6 = GPIO_LEVEL_LOW,
+ .gpio7 = GPIO_LEVEL_HIGH,
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio9 = GPIO_LEVEL_HIGH,
+ .gpio10 = GPIO_LEVEL_HIGH,
+ .gpio11 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio13 = GPIO_LEVEL_HIGH,
+ .gpio14 = GPIO_LEVEL_HIGH,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio16 = GPIO_LEVEL_HIGH,
+ .gpio17 = GPIO_LEVEL_LOW,
+ .gpio18 = GPIO_LEVEL_HIGH,
+ .gpio19 = GPIO_LEVEL_LOW,
+ .gpio20 = GPIO_LEVEL_HIGH,
+ .gpio21 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_LOW,
+ .gpio23 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio25 = GPIO_LEVEL_HIGH,
+ .gpio26 = GPIO_LEVEL_HIGH,
+ .gpio27 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+ .gpio30 = GPIO_LEVEL_HIGH,
+ .gpio31 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_blink = {
+ .gpio18 = GPIO_NO_BLINK,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio24 = GPIO_RESET_RSMRST,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE, // CLKRUN - output
+ .gpio33 = GPIO_MODE_GPIO, // SATA_DOCK_DTCT - output to SATA4GP
+ .gpio34 = GPIO_MODE_GPIO, // DGFX_VRM_ID - input - HIGH: 1GB / LOW: 2GB
+ .gpio35 = GPIO_MODE_GPIO, // pullup
+ .gpio36 = GPIO_MODE_GPIO, // pulldown
+ .gpio37 = GPIO_MODE_NATIVE, // SATA2GP - eSATA_DTCT - input to gpio
+ .gpio38 = GPIO_MODE_GPIO, // planarid2 - input - pulldown
+ .gpio39 = GPIO_MODE_GPIO, // planarid3 - input - pulldown
+ .gpio40 = GPIO_MODE_NATIVE, // OC1 - -USB_PORT1_OC1 - input
+ .gpio41 = GPIO_MODE_GPIO, // OC2 - -USB_PORTX_OC2 - input
+ .gpio42 = GPIO_MODE_GPIO, // SMB_3B_EN - output
+ .gpio43 = GPIO_MODE_NATIVE, // OC4 - pullup
+ .gpio44 = GPIO_MODE_NATIVE, // PCIECLKRQ5 - -CLKREQ_GBE - input
+ .gpio45 = GPIO_MODE_NATIVE, // PCIECLKRQ6 - -CLKREQ_USB30_TR - input
+ .gpio46 = GPIO_MODE_NATIVE, // PCIECLKRQ7 - pullup
+ .gpio47 = GPIO_MODE_NATIVE, // PEG_A_CLKRQ# - input
+ .gpio48 = GPIO_MODE_GPIO, // planarid0 - input - PDV low / FVT high
+ .gpio49 = GPIO_MODE_GPIO, // planarid1 - input - pulldown
+ .gpio50 = GPIO_MODE_GPIO, // -SC_DTCT - input
+ .gpio51 = GPIO_MODE_GPIO, // pullup
+ .gpio52 = GPIO_MODE_GPIO, // OPTIMUS_ENABLE - output - high: igpu / low: dgpu
+ .gpio53 = GPIO_MODE_GPIO, // pullup
+ .gpio54 = GPIO_MODE_GPIO, // -BDC_PRESENCE - input
+ .gpio55 = GPIO_MODE_GPIO, // pullup
+ .gpio56 = GPIO_MODE_NATIVE, // PEG_B_CLKRQ - pullup
+ .gpio57 = GPIO_MODE_GPIO, // -DTPM_PRESENCE - input
+ .gpio58 = GPIO_MODE_NATIVE, // SML1CLK - EC_SCL2 - output
+ .gpio59 = GPIO_MODE_NATIVE, // OC0 - pullup
+ .gpio60 = GPIO_MODE_NATIVE, // SML0ALERT# - pullup
+ .gpio61 = GPIO_MODE_NATIVE, // SUS_STAT - output
+ .gpio62 = GPIO_MODE_NATIVE, // SUSCLK - output
+ .gpio63 = GPIO_MODE_NATIVE, // SLP_S5 - output
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_INPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio40 = GPIO_DIR_INPUT,
+ .gpio41 = GPIO_DIR_OUTPUT,
+ .gpio42 = GPIO_DIR_OUTPUT,
+ .gpio43 = GPIO_DIR_INPUT,
+ .gpio44 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio47 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio58 = GPIO_DIR_INPUT,
+ .gpio59 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_INPUT,
+ .gpio61 = GPIO_DIR_OUTPUT,
+ .gpio62 = GPIO_DIR_OUTPUT,
+ .gpio63 = GPIO_DIR_OUTPUT,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio36 = GPIO_LEVEL_LOW,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio38 = GPIO_LEVEL_HIGH,
+ .gpio39 = GPIO_LEVEL_LOW,
+ .gpio40 = GPIO_LEVEL_HIGH,
+ .gpio41 = GPIO_LEVEL_HIGH,
+ .gpio42 = GPIO_LEVEL_HIGH,
+ .gpio43 = GPIO_LEVEL_HIGH,
+ .gpio44 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_HIGH,
+ .gpio46 = GPIO_LEVEL_HIGH,
+ .gpio47 = GPIO_LEVEL_HIGH,
+ .gpio48 = GPIO_LEVEL_HIGH,
+ .gpio49 = GPIO_LEVEL_HIGH,
+ .gpio50 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_HIGH,
+ .gpio52 = GPIO_LEVEL_HIGH,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio54 = GPIO_LEVEL_LOW,
+ .gpio55 = GPIO_LEVEL_HIGH,
+ .gpio56 = GPIO_LEVEL_HIGH,
+ .gpio57 = GPIO_LEVEL_LOW,
+ .gpio58 = GPIO_LEVEL_HIGH,
+ .gpio59 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_HIGH,
+ .gpio61 = GPIO_LEVEL_HIGH,
+ .gpio62 = GPIO_LEVEL_HIGH,
+ .gpio63 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE, // NC
+ .gpio65 = GPIO_MODE_NATIVE, // VIDEO_CLK_27M_NSS - output
+ .gpio66 = GPIO_MODE_NATIVE, // NC
+ .gpio67 = GPIO_MODE_NATIVE, // VIDEO_CLK_27M_SS - output
+ .gpio68 = GPIO_MODE_GPIO, // -INT_MIC_DTCT - input
+ .gpio69 = GPIO_MODE_GPIO, // mic enable bit - low enable - pulldown
+ .gpio70 = GPIO_MODE_GPIO, // pullup
+ .gpio71 = GPIO_MODE_GPIO, // pullup
+ .gpio72 = GPIO_MODE_NATIVE, // BATLOW - input
+ .gpio73 = GPIO_MODE_NATIVE, // pullup
+ .gpio74 = GPIO_MODE_NATIVE, // pullup
+ .gpio75 = GPIO_MODE_NATIVE, // SML1DATA - EC_SDA2 - i/o
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_OUTPUT,
+ .gpio65 = GPIO_DIR_OUTPUT,
+ .gpio66 = GPIO_DIR_OUTPUT,
+ .gpio67 = GPIO_DIR_OUTPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+ .gpio73 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_INPUT,
+ .gpio75 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_HIGH,
+ .gpio65 = GPIO_LEVEL_HIGH,
+ .gpio66 = GPIO_LEVEL_HIGH,
+ .gpio67 = GPIO_LEVEL_HIGH,
+ .gpio68 = GPIO_LEVEL_LOW,
+ .gpio69 = GPIO_LEVEL_LOW,
+ .gpio70 = GPIO_LEVEL_LOW,
+ .gpio71 = GPIO_LEVEL_HIGH,
+ .gpio72 = GPIO_LEVEL_HIGH,
+ .gpio73 = GPIO_LEVEL_HIGH,
+ .gpio74 = GPIO_LEVEL_HIGH,
+ .gpio75 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .invert = &pch_gpio_set1_invert,
+ .blink = &pch_gpio_set1_blink,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+};
diff --git a/src/mainboard/lenovo/t420/hda_verb.c b/src/mainboard/lenovo/t420/hda_verb.c
new file mode 100644
index 0000000..c37eaa8
--- /dev/null
+++ b/src/mainboard/lenovo/t420/hda_verb.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* Vendor Name : Conexant
+ * Vendor ID : 0x14f1506e
+ * Subsystem ID : 0x17aa21d2
+ * Revision ID : 0x100002
+ */
+
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 - Schematic show CX20672
+ 0x17aa21ce, // Subsystem ID
+ 0x0000000d, // Number of 4 dword sets
+
+/* Bits 31:28 - Codec Address */
+/* Bits 27:20 - NID */
+/* Bits 19:8 - Verb ID */
+/* Bits 7:0 - Payload */
+
+/* NID 0x01 - NodeInfo */
+ AZALIA_SUBVENDOR(0x0, 0x17AA21D2),
+
+ AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140),
+ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
+ AZALIA_PIN_CFG(0x0, 0x15, 0x03211020),
+ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830),
+ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),
+ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
+ AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),
+ AZALIA_PIN_CFG(0x0, 0x1d, 0x40138205),
+ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
+
+ /* Misc entries */
+ 0x00B707C0, /* Enable PortB as Output with HP amp */
+ 0x00D70740, /* Enable PortD as Output */
+ 0x0017A200, /* Disable ClkEn of PortSenseTst */
+ 0x0017C621, /* Slave Port - Port A used as microphone input for
+ combo Jack
+ Master Port - Port B used for Jack Presence Detect
+ Enable Combo Jack Detection */
+ 0x0017A208, /* Enable ClkEn of PortSenseTst */
+ 0x00170500, /* Set power state to D0 */
+ 0x00170500, /* Padding */
+ 0x00170500, /* Padding */
+};
+
+const u32 pc_beep_verbs[] = {
+ 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/t420/mainboard.c b/src/mainboard/lenovo/t420/mainboard.c
new file mode 100644
index 0000000..a5cd083
--- /dev/null
+++ b/src/mainboard/lenovo/t420/mainboard.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011-2012 Google Inc.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <drivers/intel/gma/int15.h>
+#include <arch/acpi.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <smbios.h>
+#include <device/pci.h>
+#include <pc80/keyboard.h>
+#include <ec/lenovo/h8/h8.h>
+
+static void mainboard_init(device_t dev)
+{
+ /* init spi */
+ RCBA32(0x38c8) = 0x00002005;
+ RCBA32(0x38c4) = 0x00802005;
+ RCBA32(0x38c0) = 0x00000007;
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+void h8_mainboard_init_dock(void)
+{
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c
new file mode 100644
index 0000000..8c066cb
--- /dev/null
+++ b/src/mainboard/lenovo/t420/romstage.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <console/console.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void pch_enable_lpc(void)
+{
+ /* EC Decode Range Port60/64, Port62/66 */
+ /* Enable EC, PS/2 Keyboard/Mouse */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN,
+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
+ COMA_LPC_EN);
+
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
+
+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+
+ pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000);
+}
+
+void rcba_config(void)
+{
+ /* Disable unused devices (board specific) */
+ RCBA32(FD) = 0x1ea51fe3;
+ RCBA32(BUC) = 0;
+}
+// OC3 set in bios to port 2-7, OC7 set in bios to port 10-13
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 }, /* P0 system port 4, OC0 */
+ { 1, 1, 1 }, /* P1 system port 2 (EHCI debug), OC 1 */
+ { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */
+ { 1, 0, -1 }, /* P3: WWAN, no OC */
+ { 1, 0, -1 }, /* P4: smartcard, no OC */
+ { 1, 1, -1 }, /* P5: ExpressCard, no OC */
+ { 0, 0, -1 }, /* P6: empty */
+ { 0, 0, -1 }, /* P7: empty */
+ { 1, 1, 4 }, /* P8: system port 3, OC4*/
+ { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */
+ { 1, 0, -1 }, /* P10: fingerprint reader, no OC */
+ { 1, 0, -1 }, /* P11: bluetooth, no OC. */
+ { 1, 1, -1 }, /* P12: docking, no OC */
+ { 1, 1, -1 }, /* P13: camera (LCD), no OC */
+};
+
+void mainboard_get_spd(spd_raw_data *spd) {
+ read_spd(&spd[0], 0x50);
+ read_spd(&spd[2], 0x51);
+}
diff --git a/src/mainboard/lenovo/t420/smihandler.c b/src/mainboard/lenovo/t420/smihandler.c
new file mode 100644
index 0000000..6579adb
--- /dev/null
+++ b/src/mainboard/lenovo/t420/smihandler.c
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <ec/acpi/ec.h>
+#include <ec/lenovo/h8/h8.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+#define GPE_EC_SCI 1
+#define GPE_EC_WAKE 13
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+ /* Enable 0x1600/0x1600 register pair */
+ ec_set_bit(0x00, 0x05);
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ switch (smif) {
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 1
+ * On failure, the IO Trap Handler returns a value != 1 */
+ return 1;
+}
+
+static void mainboard_smi_brightness_up(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
+}
+
+static void mainboard_smi_brightness_down(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4,
+ (value - 0x10) & 0xf0);
+}
+
+static void mainboard_smi_handle_ec_sci(void)
+{
+ u8 status = inb(EC_SC);
+ u8 event;
+
+ if (!(status & EC_SCI_EVT))
+ return;
+
+ event = ec_query();
+ printk(BIOS_DEBUG, "EC event %02x\n", event);
+
+ switch (event) {
+ case 0x14:
+ /* brightness up */
+ mainboard_smi_brightness_up();
+ break;
+ case 0x15:
+ /* brightness down */
+ mainboard_smi_brightness_down();
+ break;
+ default:
+ break;
+ }
+}
+
+void mainboard_smi_gpi(u32 gpi_sts)
+{
+ if (gpi_sts & (1 << GPE_EC_SCI))
+ mainboard_smi_handle_ec_sci();
+}
+
+int mainboard_smi_apmc(u8 data)
+{
+ switch (data) {
+ case APM_CNT_ACPI_ENABLE:
+ /* use 0x1600/0x1604 to prevent races with userspace */
+ ec_set_ports(0x1604, 0x1600);
+ /* route EC_SCI to SCI */
+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
+ provide a EC query function */
+ ec_set_ports(0x66, 0x62);
+ /* route EC_SCI to SMI */
+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ if (slp_typ == 3) {
+ u8 ec_wake = ec_read(0x32);
+ /* If EC wake events are enabled, enable wake on EC WAKE GPE. */
+ if (ec_wake & 0x14) {
+ /* Redirect EC WAKE GPE to SCI. */
+ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/t420/thermal.h b/src/mainboard/lenovo/t420/thermal.h
new file mode 100644
index 0000000..12d4399
--- /dev/null
+++ b/src/mainboard/lenovo/t420/thermal.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef T420_THERMAL_H
+#define T420_THERMAL_H
+
+ /* Temperature which OS will shutdown at */
+ #define CRITICAL_TEMPERATURE 100
+
+ /* Temperature which OS will throttle CPU */
+ #define PASSIVE_TEMPERATURE 90
+
+#endif
More information about the coreboot-gerrit
mailing list