[coreboot-gerrit] Patch set updated for coreboot: baytrail: fix missing brackets around ir_base to fix IRQ routing

Martin Roth (martinroth@google.com) gerrit at coreboot.org
Sat Nov 28 19:17:01 CET 2015


Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12525

-gerrit

commit 2e6b951a3ca10683428fffd71e77517960345278
Author: Alexander Couzens <lynxis at fe80.eu>
Date:   Tue Nov 24 09:46:18 2015 +0100

    baytrail: fix missing brackets around ir_base to fix IRQ routing
    
    The missing brackets caused other registers, including the IO APIC
    enable bit (EAN in OIC) to be overwritten. Bug introduced by
    bde6d309 (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer)
    
    Change-Id: I1d5aa2af6d74405a1a125af6221ac0e635a6b693
    Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
 src/soc/intel/baytrail/southcluster.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 49c4545..090b988 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -184,7 +184,7 @@ static void sc_init(device_t dev)
 {
 	int i;
 	u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08);
-	u16 *ir_base = (u16 *)ILB_BASE_ADDRESS + 0x20;
+	u16 *ir_base = (u16 *)(ILB_BASE_ADDRESS + 0x20);
 	u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1);
 	u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
 	const struct baytrail_irq_route *ir = &global_baytrail_irq_route;



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