[coreboot-gerrit] New patch to review for coreboot: Remove #ifdef checks on Kconfig symbols
Martin Roth (martinroth@google.com)
gerrit at coreboot.org
Fri Nov 27 21:05:50 CET 2015
Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12560
-gerrit
commit e570afd7476244fff8b03d6712f7131826db2156
Author: Martin Roth <martinroth at google.com>
Date: Fri Nov 27 13:05:04 2015 -0700
Remove #ifdef checks on Kconfig symbols
In coreboot, bool, hex, and int type symbols are ALWAYS defined.
Change-Id: I58a36b37075988bb5ff67ac692c7d93c145b0dbc
Signed-off-by: Martin Roth <martinroth at google.com>
---
src/arch/x86/acpi.c | 5 -----
src/arch/x86/include/arch/pirq_routing.h | 4 ----
src/cpu/intel/fsp_model_406dx/bootblock.c | 4 ----
src/drivers/intel/fsp1_0/cache_as_ram.inc | 4 ----
src/drivers/intel/fsp1_0/fastboot_cache.c | 4 ----
src/drivers/intel/fsp1_0/fsp_util.c | 4 ----
src/drivers/pc80/mc146818rtc_early.c | 3 ---
src/drivers/pc80/tpm/tpm.c | 5 -----
src/northbridge/amd/amdk8/coherent_ht.c | 9 ---------
src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 4 ----
src/soc/intel/fsp_baytrail/baytrail/smm.h | 4 ----
src/soc/intel/fsp_baytrail/cpu.c | 6 ------
src/soc/intel/fsp_baytrail/iosf.c | 3 ---
src/soc/intel/fsp_baytrail/nvm.c | 3 ---
src/soc/intel/fsp_baytrail/smihandler.c | 3 ---
src/soc/intel/fsp_baytrail/southcluster.c | 3 ---
16 files changed, 68 deletions(-)
diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c
index ccaab9e..2c690c4 100644
--- a/src/arch/x86/acpi.c
+++ b/src/arch/x86/acpi.c
@@ -38,11 +38,6 @@
#include <timestamp.h>
#include <romstage_handoff.h>
-/* FIXME: Kconfig doesn't support overridable defaults :-( */
-#ifndef CONFIG_HPET_MIN_TICKS
-#define CONFIG_HPET_MIN_TICKS 0x1000
-#endif
-
u8 acpi_checksum(u8 *table, u32 length)
{
u8 ret = 0;
diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h
index 542093c..d1390ba 100644
--- a/src/arch/x86/include/arch/pirq_routing.h
+++ b/src/arch/x86/include/arch/pirq_routing.h
@@ -43,10 +43,6 @@ struct irq_info {
u8 rfu;
} __attribute__((packed));
-#ifndef CONFIG_IRQ_SLOT_COUNT
-#warning "IRQ_SLOT_COUNT is not defined in Kconfig. PIRQ won't work correctly."
-#endif
-
struct irq_routing_table {
u32 signature; /* PIRQ_SIGNATURE should be here */
u16 version; /* PIRQ_VERSION */
diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c
index edbbe1b..99a27a7 100644
--- a/src/cpu/intel/fsp_model_406dx/bootblock.c
+++ b/src/cpu/intel/fsp_model_406dx/bootblock.c
@@ -45,10 +45,6 @@ static void check_for_warm_reset(void)
static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type)
{
-#ifndef CONFIG_CPU_ADDR_BITS
-#error "CONFIG_CPU_ADDR_BITS must be set."
-#endif
-
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
msr_t basem, maskm;
basem.lo = base | type;
diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc
index 24de3a8..38c8e10 100644
--- a/src/drivers/intel/fsp1_0/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc
@@ -20,10 +20,6 @@
#include <cpu/x86/post_code.h>
#include <cbmem.h>
-#ifndef CONFIG_FSP_LOC
-# error "CONFIG_FSP_LOC must be set."
-#endif
-
cmp $0, %eax
je cache_as_ram
mov $0xa0, %eax
diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c
index b836a89..5c7179e 100644
--- a/src/drivers/intel/fsp1_0/fastboot_cache.c
+++ b/src/drivers/intel/fsp1_0/fastboot_cache.c
@@ -27,10 +27,6 @@
#include <lib.h> // hexdump
#include "fsp_util.h"
-#ifndef CONFIG_VIRTUAL_ROM_SIZE
-#error "CONFIG_VIRTUAL_ROM_SIZE must be set."
-#endif
-
/* convert a pointer to flash area into the offset inside the flash */
static inline u32 to_flash_offset(void *p) {
return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE);
diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c
index ca381ff..76b882b 100644
--- a/src/drivers/intel/fsp1_0/fsp_util.c
+++ b/src/drivers/intel/fsp1_0/fsp_util.c
@@ -114,10 +114,6 @@ volatile u8 * find_fsp ()
volatile u8 *fsp_ptr;
#endif /* __PRE_RAM__ */
-#ifndef CONFIG_FSP_LOC
-#error "CONFIG_FSP_LOC must be set."
-#endif
-
/* The FSP is stored in CBFS */
fsp_ptr = (u8 *) CONFIG_FSP_LOC;
diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c
index 268cfc2..3ff5d4f 100644
--- a/src/drivers/pc80/mc146818rtc_early.c
+++ b/src/drivers/pc80/mc146818rtc_early.c
@@ -5,9 +5,6 @@
#include "option_table.h"
#endif
-#ifndef CONFIG_MAX_REBOOT_CNT
-#error "CONFIG_MAX_REBOOT_CNT not defined"
-#endif
#if CONFIG_MAX_REBOOT_CNT > 15
#error "CONFIG_MAX_REBOOT_CNT too high"
#endif
diff --git a/src/drivers/pc80/tpm/tpm.c b/src/drivers/pc80/tpm/tpm.c
index ea11095..064cb99 100644
--- a/src/drivers/pc80/tpm/tpm.c
+++ b/src/drivers/pc80/tpm/tpm.c
@@ -49,11 +49,6 @@
/* coreboot wrapper for TPM driver (end) */
-#ifndef CONFIG_TPM_TIS_BASE_ADDRESS
-/* Base TPM address standard for x86 systems */
-#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000
-#endif
-
/* the macro accepts the locality value, but only locality 0 is operational */
#define TIS_REG(LOCALITY, REG) \
(void *)(CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG)
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 6554e07..8779ec7 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -93,10 +93,6 @@
#define TRY_HIGH_FIRST 0
#endif
-#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT
- #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0
-#endif
-
#ifndef K8_HT_CHECK_PENDING_LINK
#if CONFIG_MAX_PHYSICAL_CPUS >= 4
#define K8_HT_CHECK_PENDING_LINK 1
@@ -109,11 +105,6 @@
#define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0
#endif
-#ifndef CONFIG_ENABLE_APIC_EXT_ID
- #define CONFIG_ENABLE_APIC_EXT_ID 0
-#endif
-
-
static inline void print_linkn (const char *strval, uint8_t byteval)
{
printk(BIOS_DEBUG, "%s%02x\n", strval, byteval);
diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c
index f63e0e6..08c3b0c 100644
--- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c
+++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c
@@ -24,10 +24,6 @@
#include "../chip.h"
#include <reset.h>
-#ifndef CONFIG_ENABLE_FSP_FAST_BOOT
-# error "CONFIG_ENABLE_FSP_FAST_BOOT must be set."
-#endif
-
#ifdef __PRE_RAM__
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX)
diff --git a/src/soc/intel/fsp_baytrail/baytrail/smm.h b/src/soc/intel/fsp_baytrail/baytrail/smm.h
index 0dfb488..c929572 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/smm.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/smm.h
@@ -22,10 +22,6 @@
* clobbered by the arch/x86/Kconfig if they have the same name. */
static inline int smm_region_size(void)
{
-#ifndef CONFIG_SMM_TSEG_SIZE
-#error CONFIG_SMM_TSEG_SIZE must be set.
-#endif
-
/* Make it 8MiB by default. */
if (CONFIG_SMM_TSEG_SIZE == 0)
return (8 << 20);
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index 2f6defc..5f9fc4b 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -147,9 +147,6 @@ static void adjust_apic_id_map(struct smm_loader_params *smm_params)
static void asmlinkage cpu_smm_do_relocation(void *arg)
{
-#ifndef CONFIG_MAX_CPUS
-#error CONFIG_MAX_CPUS must be set.
-#endif
msr_t smrr;
em64t100_smm_state_save_area_t *smm_state;
const struct smm_module_params *p;
@@ -204,9 +201,6 @@ static int install_relocation_handler(int num_cpus)
static int install_permanent_handler(int num_cpus)
{
-#ifndef CONFIG_SMM_RESERVED_SIZE
-#error CONFIG_SMM_RESERVED_SIZE must be set.
-#endif
/* There are num_cpus concurrent stacks and num_cpus concurrent save
* state areas. Lastly, set the stack size to the save state size. */
int save_state_size = sizeof(em64t100_smm_state_save_area_t);
diff --git a/src/soc/intel/fsp_baytrail/iosf.c b/src/soc/intel/fsp_baytrail/iosf.c
index 078e5dd..334e2dc 100644
--- a/src/soc/intel/fsp_baytrail/iosf.c
+++ b/src/soc/intel/fsp_baytrail/iosf.c
@@ -18,9 +18,6 @@
#include <baytrail/iosf.h>
#if !defined(__PRE_RAM__)
-#ifndef CONFIG_MMCONF_BASE_ADDRESS
-#error CONFIG_MMCONF_BASE_ADDRESS must be set.
-#endif
#define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12))
static inline void write_iosf_reg(int reg, uint32_t value)
diff --git a/src/soc/intel/fsp_baytrail/nvm.c b/src/soc/intel/fsp_baytrail/nvm.c
index 9c1c381..896e9b0 100644
--- a/src/soc/intel/fsp_baytrail/nvm.c
+++ b/src/soc/intel/fsp_baytrail/nvm.c
@@ -46,9 +46,6 @@ static int nvm_init(void)
/* Convert memory mapped pointer to flash offset. */
static inline uint32_t to_flash_offset(void *p)
{
-#ifndef CONFIG_ROM_SIZE
-#error CONFIG_ROM_SIZE must be set.
-#endif
return CONFIG_ROM_SIZE + (uintptr_t)p;
}
diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c
index 46da662..4d8bcc0 100644
--- a/src/soc/intel/fsp_baytrail/smihandler.c
+++ b/src/soc/intel/fsp_baytrail/smihandler.c
@@ -177,9 +177,6 @@ static void southbridge_smi_sleep(void)
*/
static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
{
-#ifndef CONFIG_MAX_CPUS
-#error CONFIG_MAX_CPUS must be set.
-#endif
em64t100_smm_state_save_area_t *state;
int node;
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
index 4d02896..6182948 100644
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -57,9 +57,6 @@ add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
static void sc_add_mmio_resources(device_t dev)
{
-#ifndef CONFIG_VIRTUAL_ROM_SIZE
-#error CONFIG_VIRTUAL_ROM_SIZE must be set.
-#endif
add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE);
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