[coreboot-gerrit] New patch to review for coreboot: build system: Add more files through cbfs-files instead of manual rules
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Thu Nov 26 18:29:59 CET 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12549
-gerrit
commit 648230987039cc32cf19d58aa1c67ee3c452f236
Author: Patrick Georgi <pgeorgi at chromium.org>
Date: Thu Nov 26 16:39:23 2015 +0100
build system: Add more files through cbfs-files instead of manual rules
verstage, romstage, and payload can be added through infrastructure now.
Change-Id: Ib9e612ae35fb8c0230175f5b8bca1b129f366f4b
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
Makefile.inc | 42 ++++++++++++++--------
src/arch/arm/Makefile.inc | 1 -
src/arch/riscv/Makefile.inc | 1 -
src/arch/x86/Makefile.inc | 12 -------
src/vendorcode/google/chromeos/vboot2/Makefile.inc | 10 +++++-
5 files changed, 36 insertions(+), 30 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index 68ba6bc..0f1a016 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -640,19 +640,12 @@ $(REFCODE_BLOB): $(RMODTOOL)
$(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@
endif
-$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $$(call strip_quotes,$$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $(REFCODE_BLOB) $$(VERSTAGE_FILE)
+$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $$(call strip_quotes,$$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $(REFCODE_BLOB)
@printf " CBFS $(subst $(obj)/,,$(@))\n"
# The full ROM may be larger than the CBFS part, so create an empty
# file (filled with \377 = 0xff) and copy the CBFS image over it.
dd if=/dev/zero bs=$(call _toint,$(CONFIG_ROM_SIZE)) count=1 2> /dev/null | tr '\000' '\377' > $@.tmp
dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null
-ifeq ($(CONFIG_PAYLOAD_NONE),y)
- @printf " PAYLOAD none (as specified by user)\n"
-endif
-ifneq ($(CONFIG_PAYLOAD_FILE),)
- @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n"
- $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) $(ADDITIONAL_PAYLOAD_CONFIG)
-endif
ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),)
ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0)
@printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n"
@@ -665,9 +658,6 @@ ifeq ($(CONFIG_CPU_MICROCODE_CBFS_GENERATE),y)
$(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES)
endif
endif
-ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
- $(CBFSTOOL) $@.tmp add-stage -f $(VERSTAGE_FILE) -n $(CONFIG_CBFS_PREFIX)/verstage $(CBFSTOOL_VERSTAGE_OPTS)
-endif
mv $@.tmp $@
@printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n"
$(CBFSTOOL) $@ print
@@ -676,11 +666,37 @@ ifeq ($(CONFIG_IASL_WARNINGS_ARE_ERRORS),)
@printf "***** Please fix the ASL for this platform. *****\n\n"
endif
+cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage
+$(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf
+$(CONFIG_CBFS_PREFIX)/romstage-type := stage
+$(CONFIG_CBFS_PREFIX)/romstage-compression := none
+ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM),y)
+$(CONFIG_CBFS_PREFIX)/romstage-options := -b 0
+endif
+ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
+# Use a 64 byte alignment to provide a minimum alignment
+# requirement for the overall romstage. While the first object within
+# romstage could have a 4 byte minimum alignment that doesn't mean the linker
+# won't decide the entire section should be aligned to a larger value. In the
+# future cbfstool should add XIP files proper and honor the alignment
+# requirements of the program segment.
+#
+# Make sure that segment for .car.data is ignored while adding romstage.
+$(CONFIG_CBFS_PREFIX)/romstage-align := 64
+$(CONFIG_CBFS_PREFIX)/romstage-options := --xip -S .car.data -P $(CONFIG_XIP_ROM_SIZE)
+endif
+
cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage
$(CONFIG_CBFS_PREFIX)/ramstage-file := $(objcbfs)/ramstage.elf
$(CONFIG_CBFS_PREFIX)/ramstage-type := stage
$(CONFIG_CBFS_PREFIX)/ramstage-compression := $(CBFS_COMPRESS_FLAG)
+cbfs-files-y += $(CONFIG_CBFS_PREFIX)/payload
+$(CONFIG_CBFS_PREFIX)/payload-file := $(CONFIG_PAYLOAD_FILE)
+$(CONFIG_CBFS_PREFIX)/payload-type := payload
+$(CONFIG_CBFS_PREFIX)/payload-compression := $(CBFS_PAYLOAD_COMPRESS_FLAG)
+$(CONFIG_CBFS_PREFIX)/payload-options := $(ADDITIONAL_PAYLOAD_CONFIG)
+
cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode
$(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB)
$(CONFIG_CBFS_PREFIX)/refcode-type := stage
@@ -717,10 +733,6 @@ bootsplash.jpg-type := bootsplash
$(obj)/coreboot.pre: $(objcbfs)/romstage.elf $(obj)/coreboot.pre1 $(CBFSTOOL)
@printf " CBFS $(subst $(obj)/,,$(@))\n"
cp $(obj)/coreboot.pre1 $@.tmp
- $(CBFSTOOL) $@.tmp add-stage \
- -f $(objcbfs)/romstage.elf \
- -n $(CONFIG_CBFS_PREFIX)/romstage -c none \
- $(CBFSTOOL_PRE_OPTS)
mv $@.tmp $@
cbfs-files-$(CONFIG_BOARD_ID_MANUAL) += board_id
diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 5af9ab8..6675360 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -23,7 +23,6 @@
ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM),y)
CBFSTOOL_PRE1_OPTS = -m arm -s $(CONFIG_CBFS_SIZE)
-CBFSTOOL_PRE_OPTS = -b 0
endif
ifeq ($(CONFIG_ARCH_ARM),y)
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 49c130b..aafce1a 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -72,7 +72,6 @@ romstage-c-ccopts += $(riscv_flags)
romstage-S-ccopts += $(riscv_asm_flags)
CBFSTOOL_PRE1_OPTS = -v -m riscv -s $(CONFIG_CBFS_SIZE)
-CBFSTOOL_PRE_OPTS = -v
endif
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 5829983..d552aa2 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -50,15 +50,6 @@ mbi.bin-type := mbi
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
CBFSTOOL_PRE1_OPTS = -m x86 -s $(CONFIG_ROM_SIZE) \
-o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) ))
-# Use a '-a 64' option to cbfstool locate to provide a minimum alignment
-# requirement for the overall romstage. While the first object within
-# romstage could have a 4 byte minimum alignment that doesn't mean the linker
-# won't decide the entire section should be aligned to a larger value. In the
-# future cbfstool should add XIP files proper and honor the alignment
-# requirements of the program segment.
-#
-# Make sure that segment for .car.data is ignored while adding romstage.
-CBFSTOOL_PRE_OPTS = -a 64 --xip -S ".car.data" -P $(CONFIG_XIP_ROM_SIZE)
endif
## Calculate the base address of CBFS for later comparisons
@@ -181,9 +172,6 @@ else
$(eval $(call early_x86_stage,verstage,elf64-x86-64))
endif
-# Verstage on x86 expected to be xip.
-CBFSTOOL_VERSTAGE_OPTS = -a 64 --xip -S ".car.data"
-
endif # CONFIG_ARCH_VERSTAGE_X86_32 / CONFIG_ARCH_VERSTAGE_X86_64
###############################################################################
diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
index 8668405..fdb0d4e 100644
--- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc
+++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc
@@ -69,7 +69,15 @@ $(VB2_LIB): $(obj)/config.h
libverstage-srcs += $(VB2_LIB)
ifeq ($(CONFIG_SEPARATE_VERSTAGE),y)
-VERSTAGE_FILE = $(objcbfs)/verstage.elf
+cbfs-files-$(CONFIG_SEPARATE_VERSTAGE) += $(CONFIG_CBFS_PREFIX)/verstage
+$(CONFIG_CBFS_PREFIX)/verstage-file := $(objcbfs)/verstage.elf
+$(CONFIG_CBFS_PREFIX)/verstage-type := stage
+# Verstage on x86 expected to be xip.
+ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
+$(CONFIG_CBFS_PREFIX)/verstage-options := -a 64 --xip -S ".car.data"
+
+endif
+
else
ifeq ($(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK),y)
bootblock-srcs += $(objgenerated)/libverstage.a
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