[coreboot-gerrit] Patch merged into coreboot/master: southbridge/amd/sr5650: Use correct PCI configuration block offset

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 56c8ef9a91b9d78ca5d1c027e21f8c7f5c96bc8b
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Fri Aug 14 02:50:44 2015 -0500

    southbridge/amd/sr5650: Use correct PCI configuration block offset
    
    Change-Id: I4277d1788d8f9a501399218544aa6d4d11349ccc
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
    Reviewed-on: https://review.coreboot.org/12049
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See https://review.coreboot.org/12049 for details.

-gerrit