[coreboot-gerrit] New patch to review for coreboot: cpu/amd: de-duplicate MSR include files
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Sun Nov 22 23:41:34 CET 2015
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12510
-gerrit
commit f89721b10f70029755b2d6f282308a7a015bb481
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date: Sun Nov 22 23:40:29 2015 +0100
cpu/amd: de-duplicate MSR include files
Change-Id: I8e01a4ab68b463efe02c27f589e0b4b719532eb5
Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
src/cpu/amd/dualcore/amd_sibling.c | 2 +-
src/cpu/amd/dualcore/dualcore_id.c | 2 +-
.../amd/family_10h-family_15h/model_10xxx_init.c | 2 +-
.../amd/family_10h-family_15h/monotonic_timer.c | 2 +-
src/cpu/amd/model_fxx/model_fxx_init.c | 2 +-
src/cpu/amd/quadcore/amd_sibling.c | 2 +-
src/cpu/amd/quadcore/quadcore_id.c | 2 +-
src/cpu/amd/smm/smm_init.c | 2 +-
src/include/cpu/amd/model_10xxx_msr.h | 45 ----------------------
src/include/cpu/amd/model_fxx_msr.h | 25 ------------
src/include/cpu/amd/msr.h | 45 ++++++++++++++++++++++
src/northbridge/amd/amdfam10/northbridge.c | 2 +-
12 files changed, 54 insertions(+), 79 deletions(-)
diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c
index d9942de..e1d4d2e 100644
--- a/src/cpu/amd/dualcore/amd_sibling.c
+++ b/src/cpu/amd/dualcore/amd_sibling.c
@@ -9,7 +9,7 @@
#include <pc80/mc146818rtc.h>
#include <smp/spinlock.h>
#include <cpu/x86/mtrr.h>
-#include <cpu/amd/model_fxx_msr.h>
+#include <cpu/amd/msr.h>
#include <cpu/amd/model_fxx_rev.h>
#include <cpu/amd/amdk8_sysconf.h>
diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c
index ba92396..4fcedae 100644
--- a/src/cpu/amd/dualcore/dualcore_id.c
+++ b/src/cpu/amd/dualcore/dualcore_id.c
@@ -3,7 +3,7 @@
#include <arch/cpu.h>
#include <cpu/amd/multicore.h>
#ifdef __PRE_RAM__
-#include <cpu/amd/model_fxx_msr.h>
+#include <cpu/amd/msr.h>
#endif
//called by bus_cpu_scan too
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
index fe9fb9c..153fb10 100644
--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
@@ -31,7 +31,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/multicore.h>
-#include <cpu/amd/model_10xxx_msr.h>
+#include <cpu/amd/msr.h>
#define MCI_STATUS 0x401
diff --git a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c b/src/cpu/amd/family_10h-family_15h/monotonic_timer.c
index 53b4c30..6bf046d 100644
--- a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c
+++ b/src/cpu/amd/family_10h-family_15h/monotonic_timer.c
@@ -21,7 +21,7 @@
#include <device/pci_ids.h>
#include <northbridge/amd/amdht/AsPsDefs.h>
-#include <cpu/amd/model_10xxx_msr.h>
+#include <cpu/amd/msr.h>
static struct monotonic_counter {
int initialized;
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index 93fa07f..1ef195d 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -26,7 +26,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/amd/multicore.h>
-#include <cpu/amd/model_fxx_msr.h>
+#include <cpu/amd/msr.h>
#if CONFIG_WAIT_BEFORE_CPUS_INIT
void cpus_ready_for_init(void)
diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c
index dc3cdbb..397a3dd 100644
--- a/src/cpu/amd/quadcore/amd_sibling.c
+++ b/src/cpu/amd/quadcore/amd_sibling.c
@@ -22,7 +22,7 @@
#include <pc80/mc146818rtc.h>
#include <smp/spinlock.h>
#include <cpu/x86/mtrr.h>
-#include <cpu/amd/model_10xxx_msr.h>
+#include <cpu/amd/msr.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
index 99e6d68..b89aac7 100644
--- a/src/cpu/amd/quadcore/quadcore_id.c
+++ b/src/cpu/amd/quadcore/quadcore_id.c
@@ -18,7 +18,7 @@
#include <arch/cpu.h>
#include <cpu/amd/multicore.h>
#ifdef __PRE_RAM__
-#include <cpu/amd/model_10xxx_msr.h>
+#include <cpu/amd/msr.h>
#endif
//called by bus_cpu_scan too
diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c
index fa81941..c87b701 100644
--- a/src/cpu/amd/smm/smm_init.c
+++ b/src/cpu/amd/smm/smm_init.c
@@ -21,7 +21,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
-#include <cpu/amd/model_fxx_msr.h>
+#include <cpu/amd/msr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
#include <string.h>
diff --git a/src/include/cpu/amd/model_10xxx_msr.h b/src/include/cpu/amd/model_10xxx_msr.h
deleted file mode 100644
index 5faf587..0000000
--- a/src/include/cpu/amd/model_10xxx_msr.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef CPU_AMD_MODEL_10XXX_MSR_H
-#define CPU_AMD_MODEL_10XXX_MSR_H
-
-#include <cpu/x86/msr.h>
-
-#define SMM_BASE_MSR 0xC0010111
-#define SMM_ADDR_MSR 0xC0010112
-#define SMM_MASK_MSR 0xC0010113
-
-#define HWCR_MSR 0xC0010015
-#define NB_CFG_MSR 0xC001001f
-#define LS_CFG_MSR 0xC0011020
-#define IC_CFG_MSR 0xC0011021
-#define DC_CFG_MSR 0xC0011022
-#define BU_CFG_MSR 0xC0011023
-#define FP_CFG_MSR 0xC0011028
-#define DE_CFG_MSR 0xC0011029
-#define BU_CFG2_MSR 0xC001102A
-#define BU_CFG3_MSR 0xC001102B
-#define EX_CFG_MSR 0xC001102C
-#define LS_CFG2_MSR 0xC001102D
-#define IBS_OP_DATA3_MSR 0xC0011037
-
-#define CPU_ID_FEATURES_MSR 0xC0011004
-#define CPU_ID_HYPER_EXT_FEATURES 0xC001100d
-#define LOGICAL_CPUS_NUM_MSR 0xC001100d
-#define CPU_ID_EXT_FEATURES_MSR 0xC0011005
-
-#endif /* CPU_AMD_MODEL_10XXX_MSR_H */
diff --git a/src/include/cpu/amd/model_fxx_msr.h b/src/include/cpu/amd/model_fxx_msr.h
deleted file mode 100644
index 2ac2d4e..0000000
--- a/src/include/cpu/amd/model_fxx_msr.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef CPU_AMD_MODEL_FXX_MSR_H
-#define CPU_AMD_MODEL_FXX_MSR_H
-
-#define SMM_BASE_MSR 0xc0010111
-#define SMM_ADDR_MSR 0xc0010112
-#define SMM_MASK_MSR 0xc0010113
-
-#define HWCR_MSR 0xC0010015
-#define NB_CFG_MSR 0xC001001f
-#define LS_CFG_MSR 0xC0011020
-#define IC_CFG_MSR 0xC0011021
-#define DC_CFG_MSR 0xC0011022
-#define BU_CFG_MSR 0xC0011023
-
-
-#define CPU_ID_FEATURES_MSR 0xc0011004
-
-/* D0 only */
-#define CPU_ID_HYPER_EXT_FEATURES 0xc001100d
-/* E0 only */
-#define LOGICAL_CPUS_NUM_MSR 0xc001100d
-
-#define CPU_ID_EXT_FEATURES_MSR 0xc0011005
-
-#endif /* CPU_AMD_MODEL_FXX_MSR_H */
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h
new file mode 100644
index 0000000..31af3e6
--- /dev/null
+++ b/src/include/cpu/amd/msr.h
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 Timothy Pearson <tpearson at raptorengineeringinc.com>, Raptor Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef CPU_AMD_MSR_H
+#define CPU_AMD_MSR_H
+
+#include <cpu/x86/msr.h>
+
+#define SMM_BASE_MSR 0xC0010111
+#define SMM_ADDR_MSR 0xC0010112
+#define SMM_MASK_MSR 0xC0010113
+
+#define HWCR_MSR 0xC0010015
+#define NB_CFG_MSR 0xC001001f
+#define LS_CFG_MSR 0xC0011020
+#define IC_CFG_MSR 0xC0011021
+#define DC_CFG_MSR 0xC0011022
+#define BU_CFG_MSR 0xC0011023
+#define FP_CFG_MSR 0xC0011028
+#define DE_CFG_MSR 0xC0011029
+#define BU_CFG2_MSR 0xC001102A
+#define BU_CFG3_MSR 0xC001102B
+#define EX_CFG_MSR 0xC001102C
+#define LS_CFG2_MSR 0xC001102D
+#define IBS_OP_DATA3_MSR 0xC0011037
+
+#define CPU_ID_FEATURES_MSR 0xC0011004
+#define CPU_ID_HYPER_EXT_FEATURES 0xC001100d
+#define LOGICAL_CPUS_NUM_MSR 0xC001100d
+#define CPU_ID_EXT_FEATURES_MSR 0xC0011005
+
+#endif /* CPU_AMD_MSR_H */
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 4826a36..17dabae 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -32,7 +32,7 @@
#include <cpu/x86/cache.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdfam10_sysconf.h>
-#include <cpu/amd/model_10xxx_msr.h>
+#include <cpu/amd/msr.h>
#include <cpu/amd/family_10h-family_15h/ram_calc.h>
#if CONFIG_LOGICAL_CPUS
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