[coreboot-gerrit] Patch set updated for coreboot: northbridge/amd/amdht: Add comment for HT Freq write ordering

[Martin Roth (martinroth@google.com)]

Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12030

-gerrit

commit 7865f9c92b5a893a9ac6d645693c82a22bd82a95
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Fri Aug 7 19:05:45 2015 -0500

    northbridge/amd/amdht: Add comment for HT Freq write ordering
    
    The BKDG is not correct regarding HT Freq write ordering;
    indicate this in a comment to avoid confusion.
    
    Change-Id: I37db191c144c81aba5d4a1e6291db5669a35a31a
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/northbridge/amd/amdht/h3ncmn.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c
index 29524af..c97d592 100644
--- a/src/northbridge/amd/amdht/h3ncmn.c
+++ b/src/northbridge/amd/amdht/h3ncmn.c
@@ -1555,6 +1555,10 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb)
 			} else {
 				temp2 = 0x0;
 			}
+			/* NOTE
+			 * The Family 15h BKDG Rev. 3.14 is wrong
+			 * Freq[4] must be set before Freq[3:0], otherwise the register writes will be ignored!
+			 */
 			if (is_gt_rev_d())
 				AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG_2, 0, 0, &temp2);
 			AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG, 11, 8, &temp);