[coreboot-gerrit] Patch set updated for coreboot: AMD/bettong: Add UART support
Zheng Bao (zheng.bao@amd.com)
gerrit at coreboot.org
Fri Nov 20 16:04:56 CET 2015
Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11749
-gerrit
commit 0b04b8b9bf08a3bd98c112c78f55d26f77556f9e
Author: Zheng Bao <fishbaozi at gmail.com>
Date: Fri Nov 20 22:48:34 2015 +0800
AMD/bettong: Add UART support
The function delay in uart8250mem.c is not enough for hudson. I guess
there are some problems in lapic_timer(). I uploaded a patch to gerrit
to show the way to enable UART feature.
http://review.coreboot.org/#/c/12343/4
Currently the HUDSON_UART is unchecked by default. Select HUDSON_UART to
enable this feature.
The UART is test at BIOS stage.
Since it is not a standart UART device, the windows internal UART driver
doesnt support it. I guess we need a driver to use it on windows.
Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb
Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
src/mainboard/amd/bettong/romstage.c | 3 +
src/southbridge/amd/agesa/hudson/acpi/uart.asl | 82 ++++++++++++++++++++++++++
src/southbridge/amd/pi/hudson/Kconfig | 16 +++++
src/southbridge/amd/pi/hudson/Makefile.inc | 5 ++
src/southbridge/amd/pi/hudson/early_setup.c | 31 ++++++++++
src/southbridge/amd/pi/hudson/hudson.h | 3 +
src/southbridge/amd/pi/hudson/uart.c | 26 ++++++++
7 files changed, 166 insertions(+)
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index 6399804..b0ec8fd 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -39,6 +39,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
+#if IS_ENABLED(CONFIG_HUDSON_UART)
+ configure_hudson_uart();
+#endif
post_code(0x31);
console_init();
}
diff --git a/src/southbridge/amd/agesa/hudson/acpi/uart.asl b/src/southbridge/amd/agesa/hudson/acpi/uart.asl
new file mode 100644
index 0000000..dcaab22
--- /dev/null
+++ b/src/southbridge/amd/agesa/hudson/acpi/uart.asl
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ Scope(\_SB.FUR0)
+ {
+ Device(UART)
+ {
+ Name(_HID, "UTK0001")
+ Name(_CID, "UARTTest")
+ Name(_UID, Zero)
+ Method(_CRS, 0, NotSerialized)
+ {
+ Name(RBUF, Buffer(0x22)
+ {
+ 0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35,
+ 0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00,
+ 0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F,
+ 0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x30, 0x00,
+ 0x79, 0x00
+ })
+ Return(RBUF)
+ }
+ Method(_STA, 0, NotSerialized)
+ {
+ If(LEqual(MWTT, Zero))
+ {
+ Return(0x0F)
+ }
+ Else
+ {
+ Return(Zero)
+ }
+ }
+ }
+ }
+/*
+ Scope(\_SB.FUR1)
+ {
+ Device(UART)
+ {
+ Name(_HID, "UTK0001")
+ Name(_CID, "UARTTest")
+ Name(_UID, One)
+ Method(_CRS, 0, NotSerialized)
+ {
+ Name(RBUF, Buffer(0x22)
+ {
+ 0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35,
+ 0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00,
+ 0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F,
+ 0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x31, 0x00,
+ 0x79, 0x00
+ })
+ Return(RBUF)
+ }
+ Method(_STA, 0, NotSerialized)
+ {
+ If(LEqual(MWTT, Zero))
+ {
+ Return(0x0F)
+ }
+ Else
+ {
+ Return(Zero)
+ }
+ }
+ }
+ }
+*/
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig
index c720791..94a313d 100644
--- a/src/southbridge/amd/pi/hudson/Kconfig
+++ b/src/southbridge/amd/pi/hudson/Kconfig
@@ -227,3 +227,19 @@ config AZ_PIN
bit 5,4 - pin 2
bit 7,6 - pin 3
endif
+
+config HUDSON_UART
+ bool "UART controller on Kern."
+ default n
+ depends on SOUTHBRIDGE_AMD_PI_KERN
+ select DRIVERS_UART_8250MEM
+ select DRIVERS_UART_8250MEM_32
+ select NO_UART_ON_SUPERIO
+ help
+ There are two UART controllers in Kern.
+ The UART registers are memory-mapped. UART
+ controller 0 registers range from FEDC_6000h
+ to FEDC_6FFFh. UART controller 1 registers
+ range from FEDC_8000h to FEDC_8FFFh.
+
+
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index fb775c5..81558d3 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -50,6 +50,11 @@ romstage-y += imc.c
ramstage-y += imc.c
endif
+ifeq ($(CONFIG_HUDSON_UART), y)
+romstage-y += uart.c
+ramstage-y += uart.c
+endif
+
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 14ffd8b..1a2f58a 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -26,6 +26,37 @@
#include "hudson.h"
#include "pci_devs.h"
+#if IS_ENABLED(CONFIG_HUDSON_UART)
+
+#include <cpu/x86/msr.h>
+#include <delay.h>
+#include <Fch/Fch.h>
+
+void configure_hudson_uart(void)
+{
+ msr_t msr;
+ u8 byte;
+
+ msr = rdmsr(0x1B);
+ msr.lo |= 1 << 11;
+ wrmsr(0x1B, msr);
+ byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2);
+ byte |= 1 << 3;
+ write8((void *)ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2, byte);
+ byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + 0x62);
+ byte |= 1 << 3;
+ write8((void *)ACPI_MMIO_BASE + AOAC_BASE + 0x62, byte);
+ write8((void *)ACPI_MMIO_BASE + 0xD00 + 0x89, 0);
+ write8((void *)ACPI_MMIO_BASE + 0xD00 + 0x8A, 0);
+ write8((void *)ACPI_MMIO_BASE + 0xD00 + 0x8E, 0);
+ write8((void *)ACPI_MMIO_BASE + 0xD00 + 0x8F, 0);
+
+ udelay(2000);
+ write8((void *)0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88, 0x01); /* reset UART */
+}
+
+#endif
+
void hudson_pci_port80(void)
{
u8 byte;
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index 6f37c90..23d9b31 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -112,6 +112,9 @@ void hudson_clk_output_48Mhz(void);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
+#if IS_ENABLED(CONFIG_HUDSON_UART)
+void configure_hudson_uart(void);
+#endif
#else
void hudson_enable(device_t dev);
diff --git a/src/southbridge/amd/pi/hudson/uart.c b/src/southbridge/amd/pi/hudson/uart.c
new file mode 100644
index 0000000..5d88204
--- /dev/null
+++ b/src/southbridge/amd/pi/hudson/uart.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/uart.h>
+
+uintptr_t uart_platform_base(int idx)
+{
+ return (uintptr_t)(0xFEDC6000 + 0x2000 * (idx & 1));
+}
+
+unsigned int uart_platform_refclk(void)
+{
+ return 48000000;
+}
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