[coreboot-gerrit] Patch set updated for coreboot: AMD/Bettong: DSDT table: Reserved MMIO space for FCH

[Zheng Bao (zheng.bao@amd.com)]

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11747

-gerrit

commit 93c6fb27626d8c77df88b56154c1f2515000372f
Author: Zheng Bao <fishbaozi at gmail.com>
Date:   Fri Nov 20 16:07:34 2015 +0800

    AMD/Bettong: DSDT table: Reserved MMIO space for FCH
    
    In current code, \_SB.PCI0 declare MMIO between TOM1 and 4GB.
    This is not correct because higher MMIO space is reserved by \_SB rather than
    \_SB.PCI0. For example:
    [0xFEDC2000 - 0xFEDC5FFF] reserved for FCH I2C
    [0xFEDC6000 - 0xFEDC8FFF] reserved for FCH UART
    
    Change-Id: I922d8c6a8ff1433582c70f86d5636171394af283
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
    Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 src/southbridge/amd/pi/hudson/acpi/fch.asl | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl
index 02a272d..18b4da2 100644
--- a/src/southbridge/amd/pi/hudson/acpi/fch.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl
@@ -108,6 +108,9 @@ Name(CRES, ResourceTemplate() {
 
 	/* memory space for PCI BARs below 4GB */
 	Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+
+	/* Reserved for FCH. 0xFED40000 - 0xFEDD0000 */
+	Memory32Fixed(ReadOnly, 0xFED40000, 0x00090000, FCHR)
 }) /* End Name(_SB.PCI0.CRES) */
 
 Method(_CRS, 0) {