[coreboot-gerrit] Patch merged into coreboot/master: AMD Bettong: refactor PCI interrupt table

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 839d68f1019f9d1a0e57b1429bf1be4685d5e095
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date:   Tue Aug 18 06:22:22 2015 +0800

    AMD Bettong: refactor PCI interrupt table
    
    1. Use write_pci_int_table to write registers 0xC00/0xC01.
    2. Add GPIO, I2C and UART interrupt according
    "BKDG for AMD Family 15h Models 60h-6Fh Processors",
    50742 Rev 3.01 - July 17, 2015
    3. The interrupt valudes are moved from bettong/mptable.c.
    All devices work in Windows 10.
    
    Change-Id: Iad13bc02c84a5dfc7c24356436ac560f593304d7
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
    Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
    Reviewed-on: http://review.coreboot.org/11746
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>
    Reviewed-by: Marc Jones <marc at marcjonesconsulting.com>


See http://review.coreboot.org/11746 for details.

-gerrit