[coreboot-gerrit] Patch merged into coreboot/master: northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 11739a48ce08d1ef11bfd54670ec23a1ee6daccd
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Thu Jun 25 18:37:45 2015 -0500

    northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue
    
    AMD Opteron processors contain a very fragile phy phase detection circuit.
    Additionally, the algorithm given in the BKDG does not function as intended;
    this was verified both on real hardware via execution trace and on paper
    with values read back from multiple CPUs and DIMMs.
    
    As a result, the phy training algorithm given in the BKDG has been
    replaced with a phy training algorithm developed at Raptor Engineering.
    This particular patch is the first part of that algorithm; the code
    is updated in future patches but this should exist in the historical
    record in case something breaks down in the later sections of code.
    
    Change-Id: Ic7a19d24954f47c922126e3da7be1f7e85f7396f
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
    Reviewed-on: http://review.coreboot.org/12007
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>


See http://review.coreboot.org/12007 for details.

-gerrit