[coreboot-gerrit] Patch set updated for coreboot: nb/intel/sandybridge/raminit: Factor out code into toggle_io_reset

[Patrick Rudolph (siro@das-labor.org)]

Patrick Rudolph (siro at das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11916

-gerrit

commit 69ecc51ce9d98a62e80c5b6919a4bda154499c2f
Author: Patrick Rudolph <siro at das-labor.org>
Date:   Fri Oct 9 13:43:51 2015 +0200

    nb/intel/sandybridge/raminit: Factor out code into toggle_io_reset
    
    Found while doing code review.
    
    Use a function to toggle IO reset signal.
    
    Change-Id: I4cb0885ed9be763fbc4069e4d015a36a7183c823
    Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
 src/northbridge/intel/sandybridge/raminit.c | 48 +++++++++--------------------
 1 file changed, 14 insertions(+), 34 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 23b34f5..4e3f93e 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -224,6 +224,15 @@ static void sfence(void)
 	asm volatile ("sfence");
 }
 
+static void toggle_io_reset(void) {
+	/* toggle IO reset bit */
+	u32 r32 = read32(DEFAULT_MCHBAR + 0x5030);
+	write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
+	udelay(1);
+	write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
+	udelay(1);
+}
+
 /*
  * Dump in the log memory controller configuration as read from the memory
  * controller registers.
@@ -1917,7 +1926,6 @@ static void read_training(ramctr_timing * ctrl)
 	int channel, slotrank, lane;
 
 	FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
-		u32 r32;
 		int all_high, some_high;
 		int upperA[NUM_LANES];
 		struct timA_minmax mnmx;
@@ -2000,12 +2008,7 @@ static void read_training(ramctr_timing * ctrl)
 
 		write32(DEFAULT_MCHBAR + 0x3400, 0);
 
-		/* toggle IO reset bit */
-		r32 = read32(DEFAULT_MCHBAR + 0x5030);
-		write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
-		udelay(1);
-		write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
-		udelay(1);
+		toggle_io_reset();
 	}
 
 	FOR_ALL_POPULATED_CHANNELS {
@@ -2530,7 +2533,6 @@ static void write_op(ramctr_timing * ctrl, int channel)
 static void write_training(ramctr_timing * ctrl)
 {
 	int channel, slotrank, lane;
-	u32 r32;
 
 	FOR_ALL_POPULATED_CHANNELS
 	    write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel,
@@ -2560,12 +2562,7 @@ static void write_training(ramctr_timing * ctrl)
 
 	write32(DEFAULT_MCHBAR + 0x3400, 0x108052);
 
-	/* toggle IO reset bit */
-	r32 = read32(DEFAULT_MCHBAR + 0x5030);
-	write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
-	udelay(1);
-	write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
-	udelay(1);
+	toggle_io_reset();
 
 	/* set any valid value for timB, it gets corrected later */
 	FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS
@@ -2601,12 +2598,7 @@ static void write_training(ramctr_timing * ctrl)
 		wait_428c(channel);
 	}
 
-	/* toggle IO reset bit */
-	r32 = read32(DEFAULT_MCHBAR + 0x5030);
-	write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
-	udelay(1);
-	write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
-	udelay(1);
+	toggle_io_reset();
 
 	printram("CPE\n");
 	precharge(ctrl);
@@ -2754,7 +2746,6 @@ static void fill_pattern5(ramctr_timing * ctrl, int channel, int patno)
 static void reprogram_320c(ramctr_timing * ctrl)
 {
 	int channel, slotrank;
-	u32 r32;
 
 	FOR_ALL_POPULATED_CHANNELS {
 		wait_428c(channel);
@@ -2804,12 +2795,7 @@ static void reprogram_320c(ramctr_timing * ctrl)
 	/* mrs commands. */
 	dram_mrscommands(ctrl);
 
-	/* toggle IO reset bit */
-	r32 = read32(DEFAULT_MCHBAR + 0x5030);
-	write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
-	udelay(1);
-	write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
-	udelay(1);
+	toggle_io_reset();
 }
 
 #define MIN_C320C_LEN 13
@@ -2995,16 +2981,10 @@ static void discover_edges(ramctr_timing * ctrl)
 	int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
 	int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
 	int channel, slotrank, lane;
-	u32 r32;
 
 	write32(DEFAULT_MCHBAR + 0x3400, 0);
 
-	/* toggle IO reset bit */
-	r32 = read32(DEFAULT_MCHBAR + 0x5030);
-	write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
-	udelay(1);
-	write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
-	udelay(1);
+	toggle_io_reset();
 
 	FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES {
 		write32(DEFAULT_MCHBAR + 4 * lane +