[coreboot-gerrit] Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12007

-gerrit

commit f3b9333f5c941ae5137790def10a725a26ebc108
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Thu Jun 25 18:37:45 2015 -0500

    northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue
    
    AMD Opteron processors contain a very fragile phy phase detection circuit.
    Additionally, the algorithm given in the BKDG does not function as intended;
    this was verified both on real hardware via execution trace and on paper
    with values read back from multiple CPUs and DIMMs.
    
    As a result, the phy training algorithm given in the BKDG has been
    replaced with a phy training algorithm developed at Raptor Engineering.
    This particular patch is the first part of that algorithm; the code
    is updated in future patches but this should exist in the historical
    record in case something breaks down in the later sections of code.
    
    Change-Id: Ic7a19d24954f47c922126e3da7be1f7e85f7396f
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
index 496803e..dfddb60 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
@@ -203,6 +203,22 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT
 
 		pDCTData->WLCriticalGrossDelayPrevPass = cgd;
 
+		if (pDCTstat->Speed != pDCTstat->TargetFreq) {
+			/* FIXME
+			 * Using the Pass 1 training values causes major phy training problems on
+			 * all Family 15h processors I tested (Pass 1 values are randomly too high,
+			 * and Pass 2 cannot lock).
+			 * Figure out why this is and fix it, then remove the bypass code below...
+			 */
+			if (pass == FirstPass) {
+				for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {
+					pDCTData->WLGrossDelay[index+ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane];
+					pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane];
+				}
+				return 0;
+			}
+		}
+
 		/* Compensate for occasional noise/instability causing sporadic training failure */
 		for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {
 			uint8_t faulty_value_detected = 0;