[coreboot-gerrit] Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Thu Nov 12 21:42:39 CET 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12007
-gerrit
commit 07891ec97f952dff9f5b46abb4846d004d35daa2
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Thu Jun 25 18:37:45 2015 -0500
northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue
Change-Id: Ic7a19d24954f47c922126e3da7be1f7e85f7396f
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
index 496803e..dfddb60 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
@@ -203,6 +203,22 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT
pDCTData->WLCriticalGrossDelayPrevPass = cgd;
+ if (pDCTstat->Speed != pDCTstat->TargetFreq) {
+ /* FIXME
+ * Using the Pass 1 training values causes major phy training problems on
+ * all Family 15h processors I tested (Pass 1 values are randomly too high,
+ * and Pass 2 cannot lock).
+ * Figure out why this is and fix it, then remove the bypass code below...
+ */
+ if (pass == FirstPass) {
+ for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {
+ pDCTData->WLGrossDelay[index+ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane];
+ pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane];
+ }
+ return 0;
+ }
+ }
+
/* Compensate for occasional noise/instability causing sporadic training failure */
for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) {
uint8_t faulty_value_detected = 0;
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