[coreboot-gerrit] New patch to review for coreboot: northbridge/amd/amdmct/mct_ddr3: Update prefetcher configuration
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Thu Nov 12 02:06:24 CET 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12417
-gerrit
commit 3c5127694d2b7d317015e84a01ced305948ee79b
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Wed Nov 11 19:01:41 2015 -0600
northbridge/amd/amdmct/mct_ddr3: Update prefetcher configuration
The existing prefetcher configuration was incorrect; use the correct
values from the AMD Family 10h and Family 15h BKDGs as appropriate.
Change-Id: I287ffa6345e1f4d232d4b2ea4251650ada3fda92
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index f696dae..b3f43fb 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -2408,9 +2408,12 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat,
} while (!(val & (1 << Dr_MemClrStatus)));
}
- val = 0x0FE40FC0; /* BKDG recommended */
+ if (is_fam15h())
+ val = 0x0ce00f41; /* BKDG recommended */
+ else
+ val = 0x0fe40fc0; /* BKDG recommended */
val |= MCCH_FlushWrOnStpGnt; /* Set for S3 */
- Set_NB32(dev, 0x11C, val);
+ Set_NB32(dev, 0x11c, val);
}
static u8 NodePresent_D(u8 Node)
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