[coreboot-gerrit] Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Clean up curly brace style violations
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Tue Nov 10 20:10:06 CET 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12360
-gerrit
commit 02050ef6ec2a27392597cae508cde9d5131ff271
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Sat Nov 7 16:23:30 2015 -0600
northbridge/amd/amdmct/mct_ddr3: Clean up curly brace style violations
Change-Id: I1ad581454e08f7a24395f50623f29ec14e07f5fb
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 63 ++++++++++-------------------
1 file changed, 21 insertions(+), 42 deletions(-)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index c0976c6..ad0e6e8 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -362,8 +362,7 @@ static uint32_t fam15h_phy_predriver_calibration_code(struct DCTStatStruc *pDCTs
else if (drive_strength == 0x3)
calibration_code = 0xfff;
}
- }
- else if (ddr_voltage_index & 0x2) {
+ } else if (ddr_voltage_index & 0x2) {
/* 1.35V */
/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 42 */
if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
@@ -397,8 +396,7 @@ static uint32_t fam15h_phy_predriver_calibration_code(struct DCTStatStruc *pDCTs
else if (drive_strength == 0x3)
calibration_code = 0xdb6;
}
- }
- else if (ddr_voltage_index & 0x1) {
+ } else if (ddr_voltage_index & 0x1) {
/* 1.5V */
/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 41 */
if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
@@ -433,8 +431,7 @@ static uint32_t fam15h_phy_predriver_calibration_code(struct DCTStatStruc *pDCTs
calibration_code = 0xb6d;
}
}
- }
- else if (package_type == PT_C3) {
+ } else if (package_type == PT_C3) {
/* Socket C32 */
if (ddr_voltage_index & 0x4) {
/* 1.25V */
@@ -480,8 +477,7 @@ static uint32_t fam15h_phy_predriver_calibration_code(struct DCTStatStruc *pDCTs
else if (drive_strength == 0x3)
calibration_code = 0xfff;
}
- }
- else if (ddr_voltage_index & 0x2) {
+ } else if (ddr_voltage_index & 0x2) {
/* 1.35V */
/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 45 */
if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
@@ -525,8 +521,7 @@ static uint32_t fam15h_phy_predriver_calibration_code(struct DCTStatStruc *pDCTs
else if (drive_strength == 0x3)
calibration_code = 0xdb6;
}
- }
- else if (ddr_voltage_index & 0x1) {
+ } else if (ddr_voltage_index & 0x1) {
/* 1.5V */
/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 44 */
if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
@@ -626,8 +621,7 @@ static uint32_t fam15h_phy_predriver_cmd_addr_calibration_code(struct DCTStatStr
else if (drive_strength == 0x3)
calibration_code = 0xb64;
}
- }
- else if (ddr_voltage_index & 0x2) {
+ } else if (ddr_voltage_index & 0x2) {
/* 1.35V */
/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 51 */
if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
@@ -661,8 +655,7 @@ static uint32_t fam15h_phy_predriver_cmd_addr_calibration_code(struct DCTStatStr
else if (drive_strength == 0x3)
calibration_code = 0x924;
}
- }
- else if (ddr_voltage_index & 0x1) {
+ } else if (ddr_voltage_index & 0x1) {
/* 1.5V */
/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 50 */
if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
@@ -743,8 +736,7 @@ static uint32_t fam15h_phy_predriver_clk_calibration_code(struct DCTStatStruc *p
else if (drive_strength == 0x3)
calibration_code = 0xff6;
}
- }
- else if (ddr_voltage_index & 0x2) {
+ } else if (ddr_voltage_index & 0x2) {
/* 1.35V */
/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 54 */
if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
@@ -778,8 +770,7 @@ static uint32_t fam15h_phy_predriver_clk_calibration_code(struct DCTStatStruc *p
else if (drive_strength == 0x3)
calibration_code = 0xdad;
}
- }
- else if (ddr_voltage_index & 0x1) {
+ } else if (ddr_voltage_index & 0x1) {
/* 1.5V */
/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 53 */
if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
@@ -848,16 +839,13 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT
else if (MemClkFreq == 0x6) {
/* DDR3-800 */
calibration_code = 0x10112222;
- }
- else if (MemClkFreq == 0xa) {
+ } else if (MemClkFreq == 0xa) {
/* DDR3-1066 */
calibration_code = 0x20112222;
- }
- else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) {
+ } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) {
/* DDR3-1333 - DDR3-1600 */
calibration_code = 0x30112222;
- }
- else if (MemClkFreq == 0x16) {
+ } else if (MemClkFreq == 0x16) {
/* DDR3-1866 */
calibration_code = 0x30332222;
}
@@ -867,16 +855,13 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT
if (MemClkFreq == 0x4) {
/* DDR3-667 */
calibration_code = 0x00112222;
- }
- else if (MemClkFreq == 0x6) {
+ } else if (MemClkFreq == 0x6) {
/* DDR3-800 */
calibration_code = 0x10112222;
- }
- else if (MemClkFreq == 0xa) {
+ } else if (MemClkFreq == 0xa) {
/* DDR3-1066 */
calibration_code = 0x20112222;
- }
- else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) {
+ } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) {
/* DDR3-1333 - DDR3-1600 */
calibration_code = 0x30112222;
}
@@ -888,20 +873,16 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT
if (MemClkFreq == 0x4) {
/* DDR3-667 */
calibration_code = 0x10222222;
- }
- else if (MemClkFreq == 0x6) {
+ } else if (MemClkFreq == 0x6) {
/* DDR3-800 */
calibration_code = 0x20222222;
- }
- else if (MemClkFreq == 0xa) {
+ } else if (MemClkFreq == 0xa) {
/* DDR3-1066 */
calibration_code = 0x30222222;
- }
- else if (MemClkFreq == 0xe) {
+ } else if (MemClkFreq == 0xe) {
/* DDR3-1333 */
calibration_code = 0x30222222;
- }
- else if (MemClkFreq == 0x12) {
+ } else if (MemClkFreq == 0x12) {
/* DDR3-1600 */
if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1))
calibration_code = 0x30222222;
@@ -1088,8 +1069,7 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc
|| (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) {
/* DDR3-667 - DDR3-1333 */
slow_access = 0;
- }
- else if (MemClkFreq == 0x12) {
+ } else if (MemClkFreq == 0x12) {
/* DDR3-1600 */
if (rank_count_dimm0 == 1)
slow_access = 0;
@@ -1105,8 +1085,7 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc
|| (MemClkFreq == 0xa)) {
/* DDR3-667 - DDR3-1066 */
slow_access = 0;
- }
- else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) {
+ } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) {
/* DDR3-1333 - DDR3-1600 */
slow_access = 1;
}
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