[coreboot-gerrit] Patch set updated for coreboot: amd/amdmct/mct_ddr3: Improve SPD DIMM detect reliability

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11975

-gerrit

commit 8baa8ce01e5c5890d1166b3fd29167d83af24e0c
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Thu Jun 4 00:10:03 2015 -0500

    amd/amdmct/mct_ddr3: Improve SPD DIMM detect reliability
    
    Upon bootup the hardware reads at minimum 256 * 16 bytes (4Kb, or 32KB) over
    I2C on a system with all DIMM slots populated.  If even one of those reads
    has a single flipped bit in it (due to EMI, cross coupling with another trace,
     or just poor margins on some cheap DIMM) the system will hang and require a
    hard reset.  In practice I've seen failure rates as high as 1 failed boot in
    50 due to this issue, granted with cheap DIMMs, but even so retrying the read
    resolves the corruption issue.
    
    I2C is not designed for continuous data transmission with high reliability, and
    there is no hardware error checking, therefore a single retry when transferring
    this amount of data makes sense.
    
    Change-Id: Ifab63eca2233c63a6a42ab8b7e742f8e47fb2a09
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 1829ff5..cef112f 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -3663,6 +3663,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
 	u8 devwidth;
 	u16 DimmSlots;
 	u8 byte = 0, bytex;
+	uint8_t crc_status;
 
 	/* preload data structure with addrs */
 	mctGet_DIMMAddr(pDCTstat, pDCTstat->Node_ID);
@@ -3683,10 +3684,20 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
 			int status;
 			smbaddr = Get_DIMMAddress_D(pDCTstat, i);
 			status = mctRead_SPD(smbaddr, SPD_ByteUse);
+			if (status >= 0) {
+				/* Verify result */
+				status = mctRead_SPD(smbaddr, SPD_ByteUse);
+			}
 			if (status >= 0) { /* SPD access is ok */
 				pDCTstat->DIMMPresent |= 1 << i;
 				read_spd_bytes(pMCTstat, pDCTstat, i);
-				if (crcCheck(pDCTstat, i)) { /* CRC is OK */
+				crc_status = crcCheck(pDCTstat, i);
+				if (!crc_status) {
+					/* Try again in case there was a transient glitch */
+					read_spd_bytes(pMCTstat, pDCTstat, i);
+					crc_status = crcCheck(pDCTstat, i);
+				}
+				if (crc_status) { /* CRC is OK */
 					byte = pDCTstat->spd_data.spd_bytes[i][SPD_TYPE];
 					if (byte == JED_DDR3SDRAM) {
 						/*Dimm is 'Present'*/