[coreboot-gerrit] Patch set updated for coreboot: cpu/amd/car: Add romstage BSP stack overrun detection
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Tue Nov 10 18:59:40 CET 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11970
-gerrit
commit e89f418e903a4c9aec49c52494ee082d614c5928
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Mon Jun 1 23:58:59 2015 -0500
cpu/amd/car: Add romstage BSP stack overrun detection
NOTE: This commit switches CacheBase in CAR to use the DCACHE_RAM_BASE
Kconfig variable. There should be no functional difference between
the existing code and the new code, however hardware verfication is
encouraged on lesser used architectures such as AMD Geode.
Change-Id: Ia2e8f99be9df388e492a633c49df21ca1c57ba13
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/cpu/amd/car/cache_as_ram.inc | 6 +++++-
src/cpu/amd/car/post_cache_as_ram.c | 8 ++++++++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 9874ec4..3295ccc 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -20,7 +20,7 @@
#include <cpu/amd/mtrr.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE
-#define CacheBase (0xd0000 - CacheSize)
+#define CacheBase CONFIG_DCACHE_RAM_BASE
#define CacheSizeBSPStack CONFIG_DCACHE_BSP_STACK_SIZE
#define CacheSizeBSPSlush CONFIG_DCACHE_BSP_STACK_SLUSH
@@ -496,6 +496,10 @@ CAR_skip_k8_errata_part2:
movl $(CacheBase + CacheSize), %eax
movl %eax, %esp
+ /* Poison the lower stack boundary */
+ movl $((CacheBase + CacheSize) - CacheSizeBSPStack), %eax
+ movl $0xdeadbeef, (%eax)
+
post_code(0xa3)
jmp CAR_FAM10_ap_out
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 49b9ee3..26e611c 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -98,6 +98,14 @@ void post_cache_as_ram(void)
void *resume_backup_memory = NULL;
uint32_t family = amd_fam1x_cpu_family();
+ /* Verify that the BSP didn't overrun the lower stack
+ * boundary during romstage execution
+ */
+ volatile uint32_t *lower_stack_boundary;
+ lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_DCACHE_BSP_STACK_SIZE);
+ if ((*lower_stack_boundary) != 0xdeadbeef)
+ printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n");
+
struct romstage_handoff *handoff;
handoff = romstage_handoff_find_or_add();
if (handoff != NULL)
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