[coreboot-gerrit] Patch set updated for coreboot: AMD/Bettong: Memory configuration for DDR3 and DDR4
Zheng Bao (zheng.bao@amd.com)
gerrit at coreboot.org
Tue Nov 10 09:37:31 CET 2015
Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11733
-gerrit
commit 368b18def58cff0c67c7118517b6ebf036ca031d
Author: Zheng Bao <fishbaozi at gmail.com>
Date: Mon Nov 9 23:57:45 2015 +0800
AMD/Bettong: Memory configuration for DDR3 and DDR4
1. Bettong Rev A-E are DDR3, Bettong Rev F is DDR4.
2. DDR4 uses different memory configuration in AGESA.
Pass memory configuration parameters in agesawrapper_amdinitpost.
3. Tested on Rev C and Rev F.
Both of them can boot to Windows 8 and have the correct memory size.
Change-Id: Ia0d35ebf1b65c399abc3777ee6bdb107437a4345
Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
src/mainboard/amd/bettong/BiosCallOuts.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c
index e14978a..35c3d3a 100644
--- a/src/mainboard/amd/bettong/BiosCallOuts.c
+++ b/src/mainboard/amd/bettong/BiosCallOuts.c
@@ -27,6 +27,9 @@
#include "hudson.h"
#include <stdlib.h>
#include "BiosCallOuts.h"
+#include "northbridge/amd/pi/agesawrapper.h"
+#include <PlatformMemoryConfiguration.h>
+#include <boardid.h>
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
@@ -91,3 +94,26 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
return AGESA_SUCCESS;
}
+
+/* NOTE: Only for Bettong. */
+#ifdef __PRE_RAM__
+
+const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
+ DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+ MOTHER_BOARD_LAYERS (LAYERS_6),
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+ PSO_END
+};
+
+void OemPostParams(AMD_POST_PARAMS *PostParams)
+{
+ if (board_id() == 'F') {
+ PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
+ }
+}
+#endif
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