[coreboot-gerrit] New patch to review for coreboot: [REMOVAL] iwill/dk8s2
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Mon Nov 9 22:45:51 CET 2015
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12372
-gerrit
commit 09195a058f389ce77e29fae6dd04b9c2e349d6a5
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date: Mon Nov 9 13:32:31 2015 -0800
[REMOVAL] iwill/dk8s2
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.
Change-Id: I4a942150590fb69ff97279ff2b48b3be83abafa4
Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
src/mainboard/iwill/dk8s2/Kconfig | 52 ----------
src/mainboard/iwill/dk8s2/Kconfig.name | 2 -
src/mainboard/iwill/dk8s2/board_info.txt | 2 -
src/mainboard/iwill/dk8s2/cmos.layout | 60 -----------
src/mainboard/iwill/dk8s2/devicetree.cb | 75 --------------
src/mainboard/iwill/dk8s2/irq_tables.c | 41 --------
src/mainboard/iwill/dk8s2/mptable.c | 166 -------------------------------
src/mainboard/iwill/dk8s2/romstage.c | 164 ------------------------------
8 files changed, 562 deletions(-)
diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig
deleted file mode 100644
index 6b54645..0000000
--- a/src/mainboard/iwill/dk8s2/Kconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-if BOARD_IWILL_DK8S2
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_940
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_AMD_AMD8111
- select SOUTHBRIDGE_AMD_AMD8131
- select SUPERIO_WINBOND_W83627HF
- select PARALLEL_CPU_INIT
- select HAVE_PIRQ_TABLE
- select HAVE_OPTION_TABLE
- select HAVE_MP_TABLE
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select DRIVERS_ATI_RAGEXL
- select BOARD_ROMSIZE_KB_512
- select RAMINIT_SYSINFO
- select QRANK_DIMM_SUPPORT
-
-config MAINBOARD_DIR
- string
- default iwill/dk8s2
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-config MAINBOARD_PART_NUMBER
- string
- default "DK8S2"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x1
-
-config IRQ_SLOT_COUNT
- int
- default 12
-
-endif # BOARD_IWILL_DK8S2
diff --git a/src/mainboard/iwill/dk8s2/Kconfig.name b/src/mainboard/iwill/dk8s2/Kconfig.name
deleted file mode 100644
index ff5a685..0000000
--- a/src/mainboard/iwill/dk8s2/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_IWILL_DK8S2
- bool "DK8S2"
diff --git a/src/mainboard/iwill/dk8s2/board_info.txt b/src/mainboard/iwill/dk8s2/board_info.txt
deleted file mode 100644
index d84d5c8..0000000
--- a/src/mainboard/iwill/dk8s2/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: server
-Board URL: http://web.archive.org/web/20060509143427/http://www.iwill.net/product_2.asp?p_id=42&sp=Y
diff --git a/src/mainboard/iwill/dk8s2/cmos.layout b/src/mainboard/iwill/dk8s2/cmos.layout
deleted file mode 100644
index 4e081ea..0000000
--- a/src/mainboard/iwill/dk8s2/cmos.layout
+++ /dev/null
@@ -1,60 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/iwill/dk8s2/devicetree.cb b/src/mainboard/iwill/dk8s2/devicetree.cb
deleted file mode 100644
index 21eadb3..0000000
--- a/src/mainboard/iwill/dk8s2/devicetree.cb
+++ /dev/null
@@ -1,75 +0,0 @@
-chip northbridge/amd/amdk8/root_complex
- device cpu_cluster 0 on
- chip cpu/amd/socket_940
- device lapic 0 on end
- end
- end
- device domain 0 on
- subsystemid 0x161f 0x3016 inherit
- chip northbridge/amd/amdk8
- device pci 18.0 on # LDT 0
- chip southbridge/amd/amd8131
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 1.0 on end
- device pci 1.1 on end
- end
- chip southbridge/amd/amd8111
- # this "device pci 0.0" is the parent the next one
- # PCI bridge
- device pci 0.0 on
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 0.2 on end
- device pci 1.0 off end
- end
- device pci 1.0 on
- chip superio/winbond/w83627hf
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off end # CIR
- device pnp 2e.7 off end # GAME_MIDI_GIPO1
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- end
- end
- end
- device pci 1.1 on end
- device pci 1.2 on end
- device pci 1.3 on end
- device pci 1.5 off end
- device pci 1.6 off end
- end
- end # LDT0
- device pci 18.0 on end # LDT1
- device pci 18.0 on end # LDT2
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/iwill/dk8s2/irq_tables.c b/src/mainboard/iwill/dk8s2/irq_tables.c
deleted file mode 100644
index 3e1424c..0000000
--- a/src/mainboard/iwill/dk8s2/irq_tables.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* This file was generated by getpir.c, do not modify!
- (but if you do, please run checkpir on it to verify)
- * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
- *
- * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x07<<3)|0x3, /* Where the interrupt router lies (dev) */
- 0, /* IRQs devoted exclusively to PCI usage */
- 0x1022, /* Vendor */
- 0x746b, /* Device */
- 0, /* Miniport data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x6d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x07<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x0, 0x0},
- {0x03,(0x00<<3)|0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x04, 0x0def8}}, 0x0, 0x0},
- {0x02,(0x01<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x1, 0x0},
- {0x02,(0x02<<3)|0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x2, 0x0},
- {0x01,(0x01<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x3, 0x0},
- {0x01,(0x02<<3)|0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x4, 0x0},
- {0x03,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x5, 0x0},
- {0x03,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x6, 0x0},
- {0x03,(0x06<<3)|0x0, {{0x03, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x02,(0x03<<3)|0x0, {{0x04, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x02,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x02,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- }
-};
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/iwill/dk8s2/mptable.c b/src/mainboard/iwill/dk8s2/mptable.c
deleted file mode 100644
index b460ff7..0000000
--- a/src/mainboard/iwill/dk8s2/mptable.c
+++ /dev/null
@@ -1,166 +0,0 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
- unsigned char bus_8131_1;
- unsigned char bus_8131_2;
- unsigned char bus_8111_1;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- {
- device_t dev;
-
- /* 8111 */
- dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
- if (dev) {
- bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
- bus_8111_1 = 4;
- }
- /* 8131-1 */
- dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
- if (dev) {
- bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
- bus_8131_1 = 2;
- }
- /* 8131-2 */
- dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
- if (dev) {
- bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
- bus_8131_2 = 3;
- }
- }
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x11, VIO_APIC_VADDR);
- {
- device_t dev;
- struct resource *res;
- /* 8131 apic 3 */
- dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 0x03, 0x11,
- res2mmio(res, 0, 0));
- }
- }
- /* 8131 apic 4 */
- dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 0x04, 0x11,
- res2mmio(res, 0, 0));
- }
- }
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
-
- /* Standard local interrupt assignments */
- mptable_lintsrc(mc, bus_isa);
-
-
- /* PCI Slot 1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|0, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|1, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|2, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|3, 0x02, 0x10);
-
- /* PCI Slot 2 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|0, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|1, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|2, 0x02, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|3, 0x02, 0x11);
-
- /* PCI Slot 3 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|0, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|1, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|2, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|3, 0x02, 0x10);
-
- /* PCI Slot 4 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|0, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|1, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|2, 0x02, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|3, 0x02, 0x11);
-
- /* PCI Slot 5 */
- // FIXME get the irqs right, it's just hacked to work for now
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (5<<2)|0, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (5<<2)|1, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (5<<2)|2, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (5<<2)|3, 0x02, 0x10);
-
- /* PCI Slot 6 */
- // FIXME get the irqs right, it's just hacked to work for now
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (4<<2)|0, 0x02, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (4<<2)|1, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (4<<2)|2, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (4<<2)|3, 0x02, 0x13);
-
- /* On board nics */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (3<<2)|0, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (4<<2)|0, 0x02, 0x13);
-
- /* There is no extension information... */
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
deleted file mode 100644
index 601c649..0000000
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ /dev/null
@@ -1,164 +0,0 @@
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/early_smbus.c"
-#include <northbridge/amd/amdk8/raminit.h>
-#include "northbridge/amd/amdk8/reset_test.c"
-#include <cpu/x86/bist.h>
-#include <delay.h>
-#include "northbridge/amd/amdk8/debug.c"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "southbridge/amd/amd8111/early_ctrl.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-/*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
-static void memreset_setup(void)
-{
- if (is_cpu_pre_c0()) {
- /* Set the memreset low. */
- outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines. */
- outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
- } else {
- /* Ensure the CPU has control of the memory lines. */
- outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
- }
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- if (is_cpu_pre_c0()) {
- udelay(800);
- /* Set memreset high. */
- outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
- udelay(90);
- }
-}
-
-static void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <spd.h>
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- // first node
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
-
- // second node
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
-
- struct sys_info *sysinfo = &sysinfo_car;
- int needs_reset;
- unsigned bsp_apicid = 0;
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-
- setup_default_resource_map();
-
- printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-
- setup_coherent_ht_domain(); // routing table and start other core0
-
- wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS
- // It is said that we should start core1 after all core0 launched
- /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
- * So here need to make sure last core0 is started, esp for two way system,
- * (there may be apic id conflicts in that case)
- */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-
-#if CONFIG_SET_FIDVID
- {
- msr_t msr;
- msr=rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
- {
- msr_t msr;
- msr=rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- }
-#endif
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
-
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- //It's the time to set ctrl in sysinfo now;
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
-
-#if 0
- dump_smbus_registers();
-#endif
-
- memreset_setup();
-
- //do we need apci timer, tsc...., only debug need it for better output
- /* all ap stopped? */
- init_timer(); // Need to use TMICT to synchronize FID/VID
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
-#if 0
- dump_pci_devices();
-#endif
-
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-}
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