[coreboot-gerrit] Patch set updated for coreboot: AMD/Bettong: Memory configuration for DDR3 and DDR4

[Zheng Bao (zheng.bao@amd.com)]

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11733

-gerrit

commit b22d76311bf32d48663eb22b3045523cacb7bee4
Author: zbao <fishbaozi at gmail.com>
Date:   Fri Nov 6 17:55:01 2015 +0800

    AMD/Bettong: Memory configuration for DDR3 and DDR4
    
    1. Bettong Rev A-E are DDR3, Bettong Rev F is DDR4.
    
    2. DDR4 uses different memory configuration in AGESA.
    Pass memory configuration parameters in agesawrapper_amdinitpost.
    
    3. Tested on Rev C and Rev F.
    Both of them can boot to Windows 8 and have the correct memory size.
    
    Change-Id: Ia0d35ebf1b65c399abc3777ee6bdb107437a4345
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
    Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 src/mainboard/amd/bettong/BiosCallOuts.c | 16 +++++++++++++++
 src/northbridge/amd/pi/agesawrapper.c    | 35 ++++++++++++++++++++++++++++++++
 src/northbridge/amd/pi/agesawrapper.h    |  2 ++
 3 files changed, 53 insertions(+)

diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c
index e14978a..77d29ce 100644
--- a/src/mainboard/amd/bettong/BiosCallOuts.c
+++ b/src/mainboard/amd/bettong/BiosCallOuts.c
@@ -27,6 +27,8 @@
 #include "hudson.h"
 #include <stdlib.h>
 #include "BiosCallOuts.h"
+#include "northbridge/amd/pi/agesawrapper.h"
+#include <boardid.h>
 
 static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
 
@@ -91,3 +93,17 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
 
 	return AGESA_SUCCESS;
 }
+
+/* NOTE: Only for Bettong. */
+#ifdef __PRE_RAM__
+TECHNOLOGY_TYPE get_mainboard_dimmtype(void)
+{
+	if (board_id() == 'F') {
+		return DDR4_TECHNOLOGY;
+	} else {
+		return DDR3_TECHNOLOGY;
+	}
+
+	return UNSUPPORTED_TECHNOLOGY; /* not reached here. */
+}
+#endif
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c
index 5772fb4..6c2cf12 100644
--- a/src/northbridge/amd/pi/agesawrapper.c
+++ b/src/northbridge/amd/pi/agesawrapper.c
@@ -22,6 +22,7 @@
 #include <heapManager.h>
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/BiosCallOuts.h>
+#include <PlatformMemoryConfiguration.h>
 
 VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
 VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
@@ -42,6 +43,11 @@ static void *AcpiIvrs    = NULL;
 static void *AcpiCrat    = NULL;
 #endif /* #ifndef __PRE_RAM__ */
 
+TECHNOLOGY_TYPE __attribute__((weak)) get_mainboard_dimmtype(void)
+{
+	return DDR3_TECHNOLOGY;
+}
+
 AGESA_STATUS agesawrapper_amdinitreset(void)
 {
 	AGESA_STATUS status;
@@ -132,6 +138,35 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
 	AmdCreateStruct (&AmdParamStruct);
 	PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
 
+	PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
+		DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
+		NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+		NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+		MOTHER_BOARD_LAYERS (LAYERS_6),
+		MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+		CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+		ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+		CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+		PSO_END
+	};
+
+	PSO_ENTRY DDR3PlatformMemoryConfiguration[] = {
+		DRAM_TECHNOLOGY(ANY_SOCKET, DDR3_TECHNOLOGY),
+		NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+		NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+		MOTHER_BOARD_LAYERS (LAYERS_6),
+		MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+		CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+		ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
+		CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+		PSO_END
+	};
+
+	if (get_mainboard_dimmtype() == DDR4_TECHNOLOGY)
+		PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
+	else
+		PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR3PlatformMemoryConfiguration;
+
 	// Do not use IS_ENABLED here.  CONFIG_GFXUMA should always have a value.  Allow
 	// the compiler to flag the error if CONFIG_GFXUMA is not set.
 	PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE;
diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h
index cba7dc6..bd9f71f 100644
--- a/src/northbridge/amd/pi/agesawrapper.h
+++ b/src/northbridge/amd/pi/agesawrapper.h
@@ -58,4 +58,6 @@ VOID amd_initcpuio(void);
 VOID amd_initmmio(void);
 const void *agesawrapper_locate_module (const CHAR8 name[8]);
 
+TECHNOLOGY_TYPE get_mainboard_dimmtype(void);
+
 #endif /* _AGESAWRAPPER_H_ */