[coreboot-gerrit] Patch set updated for coreboot: fsp_baytrail: Add functions to set a GPIO

[Werner Zeh (werner.zeh@siemens.com)]

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12341

-gerrit

commit 155b1fc6035a067d6b7b73ec792bec22ad5da509
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Fri Nov 6 08:38:38 2015 +0100

    fsp_baytrail: Add functions to set a GPIO
    
    Add two functions to set a memory mapped GPIO to a given value.
    
    TEST=Booted siemens/mc_tcu3 board and confirmed GPIO-value after
         using this functions.
    
    Change-Id: Idc14c5d4049487e60040cc294ba0cea363d998a6
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/soc/intel/fsp_baytrail/baytrail/gpio.h | 18 ++++++++++++++++++
 src/soc/intel/fsp_baytrail/gpio.c          | 24 ++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
index 15f65ee..3d30a86 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
@@ -336,7 +336,9 @@ void setup_soc_gpios(struct soc_gpio_config *config);
 /* This function is weak and can be overridden by a mainboard function. */
 struct soc_gpio_config* mainboard_get_gpios(void);
 uint8_t read_score_gpio(uint8_t gpio_num);
+void write_score_gpio(uint8_t gpio_num, uint8_t val);
 uint8_t read_ssus_gpio(uint8_t gpio_num);
+void write_ssus_gpio(uint8_t gpio_num, uint8_t val);
 void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
 void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
 
@@ -398,6 +400,22 @@ static inline int ssus_get_gpio(int pad)
 	return read32(val_addr) & PAD_VAL_HIGH;
 }
 
+/* These functions require that the output pad is configured as an output */
+/* GPIO and is mapped to memory space and not IO space. */
+static inline void score_set_gpio(int pad, int val)
+{
+	uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
+
+	write32(val_addr, ((read32(val_addr) & ~0x1) | val));
+}
+
+static inline void ssus_set_gpio(int pad, int val)
+{
+	uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
+
+	write32(val_addr, ((read32(val_addr) & ~0x1) | val));
+}
+
 static inline void ssus_disable_internal_pull(int pad)
 {
 	const uint32_t pull_mask = ~(0xf << 7);
diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c
index 6313596..3497a63 100644
--- a/src/soc/intel/fsp_baytrail/gpio.c
+++ b/src/soc/intel/fsp_baytrail/gpio.c
@@ -266,6 +266,18 @@ uint8_t read_score_gpio(uint8_t gpio_num)
 	return retval;
 }
 
+/** \brief sets an output SCORE GPIO to desired value
+ *
+ * @param gpio_num The GPIO number being read
+ * @param val The value this output must be set to (0 or 1)
+ * @return void
+ */
+void write_score_gpio(uint8_t gpio_num, uint8_t val)
+{
+	if (gpio_num < GPSCORE_COUNT)
+		score_set_gpio(gpscore_gpio_to_pad[gpio_num], val);
+}
+
 /** \brief returns the input / output value from an SSUS GPIO
  *
  * @param gpio_num The GPIO number being read
@@ -280,6 +292,18 @@ uint8_t read_ssus_gpio(uint8_t gpio_num)
 	return retval;
 }
 
+/** \brief sets an output SSUS GPIO to desired value
+ *
+ * @param gpio_num The GPIO number being read
+ * @param val The value this output must be set to (0 or 1)
+ * @return void
+ */
+void write_ssus_gpio(uint8_t gpio_num, uint8_t val)
+{
+	if (gpio_num < GPSSUS_COUNT)
+		ssus_set_gpio(gpssus_gpio_to_pad[gpio_num], val);
+}
+
 /** \brief Sets up the function, pulls, and Input/Output of a Baytrail
  *         SSUS (S5) or SCORE (S0) GPIO
  *