[coreboot-gerrit] New patch to review for coreboot: fsp_baytrail: Add macros for legacy GPIO output set up

[Werner Zeh (werner.zeh@siemens.com)]

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12340

-gerrit

commit 93dd990e9b296b4dd5944f6bb7048406ab4509e3
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Fri Nov 6 08:22:22 2015 +0100

    fsp_baytrail: Add macros for legacy GPIO output set up
    
    Up to now the GPIO set up macros for input sets up GPIOs to be
    mapped to memory space while macros for outputs sets up GPIOs
    to be mapped to legacy io space. This patch adds two additional
    macros for legacy output definition and changes the old macros
    to memory space mapping.
    
    In addition, the intel/minnowmax mainboard is modified to use
    the legacy macros for outputs to ensure this mainboard stays
    unchanged in terms of functionality.
    
    TEST=Bootet siemens/mc_tcu3 and ensured GPIO set up in linux.
    
    Change-Id: I99e98d31e1a59e63c58d536f2c493d6dcbfd1e75
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/mainboard/intel/minnowmax/gpio.c       |  6 +++---
 src/soc/intel/fsp_baytrail/baytrail/gpio.h | 21 +++++++++++++++++++--
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c
index 12d3aeb..008dbee 100644
--- a/src/mainboard/intel/minnowmax/gpio.c
+++ b/src/mainboard/intel/minnowmax/gpio.c
@@ -178,9 +178,9 @@ static const struct soc_gpio_map gpssus_gpio_map[] = {
 	GPIO_INPUT,				/* GPIO_S5[05] - BOM_OP1 - Memory: 0=1GB 1=2GB or 4GB*/
 	GPIO_INPUT,				/* GPIO_S5[06] - BOM_OP2 */
 	GPIO_INPUT,				/* GPIO_S5[07] - BOM_OP3 */
-	GPIO_OUT_HIGH,				/* GPIO_S5[08] - SOC_USB_HOST_EN0 */
-	GPIO_OUT_HIGH,				/* GPIO_S5[09] - SOC_USB_HOST_EN1 */
-	GPIO_OUT_HIGH,				/* GPIO_S5[10] - GPIO_S5_10_UNLOCK */
+	GPIO_OUT_HIGH_LEGACY,		/* GPIO_S5[08] - SOC_USB_HOST_EN0 */
+	GPIO_OUT_HIGH_LEGACY,		/* GPIO_S5[09] - SOC_USB_HOST_EN1 */
+	GPIO_OUT_HIGH_LEGACY,		/* GPIO_S5[10] - GPIO_S5_10_UNLOCK */
 	GPIO_FUNC0,				/* GPIO_S5[11] - SUSPWRDNACK (TP14) */
 	GPIO_FUNC0,				/* GPIO_S5[12] - PMC_SUSCLK0 */
 	GPIO_FUNC1,				/* GPIO_S5[13] - PMC_SLP_S0IX (TP10) */
diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
index 15f65ee..a3fbf5d 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
@@ -202,12 +202,29 @@
 	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
 	  .pad_val   = PAD_VAL_INPUT, }
 
+#define GPIO_OUT_LOW_LEGACY \
+	{ .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
+	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
+	  .pad_val   = PAD_VAL_OUTPUT | PAD_VAL_LOW, \
+	  .use_sel   = GPIO_USE_LEGACY, \
+	  .io_sel    = GPIO_DIR_OUTPUT, \
+	  .gp_lvl    = GPIO_LEVEL_LOW, \
+	  .is_gpio   = 1 }
+
+#define GPIO_OUT_HIGH_LEGACY \
+	{ .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
+	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
+	  .pad_val   = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \
+	  .use_sel   = GPIO_USE_LEGACY, \
+	  .io_sel    = GPIO_DIR_OUTPUT, \
+	  .gp_lvl    = GPIO_LEVEL_HIGH, \
+	  .is_gpio   = 1 }
 
 #define GPIO_OUT_LOW \
 	{ .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
 	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
 	  .pad_val   = PAD_VAL_OUTPUT | PAD_VAL_LOW, \
-	  .use_sel   = GPIO_USE_LEGACY, \
+	  .use_sel   = GPIO_USE_MMIO, \
 	  .io_sel    = GPIO_DIR_OUTPUT, \
 	  .gp_lvl    = GPIO_LEVEL_LOW, \
 	  .is_gpio   = 1 }
@@ -216,7 +233,7 @@
 	{ .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
 	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
 	  .pad_val   = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \
-	  .use_sel   = GPIO_USE_LEGACY, \
+	  .use_sel   = GPIO_USE_MMIO, \
 	  .io_sel    = GPIO_DIR_OUTPUT, \
 	  .gp_lvl    = GPIO_LEVEL_HIGH, \
 	  .is_gpio   = 1 }