[coreboot-gerrit] Patch set updated for coreboot: fsp_baytrail: use external microcode .h files
Martin Roth (martinroth@google.com)
gerrit at coreboot.org
Thu Nov 5 21:46:48 CET 2015
Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12334
-gerrit
commit c8159e7aa971a53488dd6f5eba8410186dfb7725
Author: Martin Roth <martinroth at google.com>
Date: Thu Nov 5 08:06:54 2015 -0700
fsp_baytrail: use external microcode .h files
The microcode for Bay Trail that's in the blobs repo is for the
M and D chip variants only. The fsp_baytrail directory is for
Bay Trail I chip variants, and will not boot if the M/D microcode
is used. The microcode for the I variant is supplied as part
of the Bay Trail FSP package.
Change-Id: I5493deb1626dc3cf037053e13e092f5a1143a13a
Signed-off-by: Martin Roth <martinroth at google.com>
---
src/soc/intel/fsp_baytrail/Kconfig | 7 +++++++
src/soc/intel/fsp_baytrail/Makefile.inc | 2 --
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index 7e7f217..ff23308 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -46,6 +46,9 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_INTEL_FIRMWARE
select HAVE_SPI_CONSOLE_SUPPORT
+ # Microcode header files are delivered in FSP package
+ select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN
+
config SOC_INTEL_FSP_BAYTRAIL_MD
bool
default n
@@ -98,6 +101,10 @@ config VGA_BIOS_FILE
string
default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS
+config CPU_MICROCODE_HEADER_FILES
+ string
+ default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h"
+
## Baytrail Specific FSP Kconfig
source src/soc/intel/fsp_baytrail/fsp/Kconfig
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index e52bceb..215f860 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -54,8 +54,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c
ramstage-y += placeholders.c
ramstage-y += i2c.c
-cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
-
CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/
CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
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