[coreboot-gerrit] Patch merged into coreboot/master: fsp1_1: pass ROM_SIZE to FSP for cacheable RO region
gerrit at coreboot.org
gerrit at coreboot.org
Thu Nov 5 17:40:08 CET 2015
the following patch was just integrated into master:
commit 2524be4aff63e01637d28d6866fa23a513a3b8b1
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Oct 29 10:43:21 2015 -0500
fsp1_1: pass ROM_SIZE to FSP for cacheable RO region
As vboot verification works on regions outside of CBFS
pass the entire ROM_SIZE to FSP for creating a cacheable
RO region.
Additionally remove the CACHE_ROM_SIZE_OVERRIDE as it doesn't
work with non-power of 2 CBFS_SIZE. In practice the entire
ROM should be attempted to be cached.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados w/ a 3MiB CBFS_SIZE.
Change-Id: I61404c626ab2bcfd039d6eb3c01d9c13a0928446
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 92568c630c48446b1ad9d4f22056f22e0679970c
Original-Change-Id: I032e4d615d2b68d3a2e597555eb1b5034a74bf0a
Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309770
Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Reviewed-on: http://review.coreboot.org/12260
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
See http://review.coreboot.org/12260 for details.
-gerrit
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