[coreboot-gerrit] Patch set updated for coreboot: AMD Bettong: Enable S4 feature for Windows 7

[Zheng Bao (zheng.bao@amd.com)]

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11373

-gerrit

commit ead415ec96f058d21dd7b8fc7d8ae87405158c9a
Author: zbao <fishbaozi at gmail.com>
Date:   Thu Nov 5 20:25:59 2015 +0800

    AMD Bettong: Enable S4 feature for Windows 7
    
    PMIOxEE is for setting USB3 power rail. Set it to S0, otherwise
    going into hibernation can not be wake up.
    
    Change-Id: I692497bad24d745738d670897e725a568c1db114
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
 src/arch/x86/acpi.c                  | 6 ++++++
 src/arch/x86/include/arch/acpi.h     | 2 ++
 src/mainboard/amd/bettong/romstage.c | 6 ++++++
 3 files changed, 14 insertions(+)

diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c
index 55995c9..c540b5c 100644
--- a/src/arch/x86/acpi.c
+++ b/src/arch/x86/acpi.c
@@ -1005,6 +1005,12 @@ int acpi_is_wakeup_s3(void)
 	return (acpi_slp_type == 3);
 }
 
+int acpi_is_wakeup_s4(void)
+{
+	acpi_handoff_wakeup();
+	return (acpi_slp_type == 4);
+}
+
 void acpi_fail_wakeup(void)
 {
 	if (acpi_slp_type == 3 || acpi_slp_type == 2)
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 66e1100..87810b6 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -596,12 +596,14 @@ static inline int acpi_is_wakeup_s3(void)
 #else
 int acpi_is_wakeup(void);
 int acpi_is_wakeup_s3(void);
+int acpi_is_wakeup_s4(void);
 #endif
 
 #else
 #define acpi_slp_type 0
 static inline int acpi_is_wakeup(void) { return 0; }
 static inline int acpi_is_wakeup_s3(void) { return 0; }
+static inline int acpi_is_wakeup_s4(void) { return 0; }
 #endif
 
 #endif  /* __ASM_ACPI_H */
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index 9f94d7b..6399804 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -15,6 +15,7 @@
 
 #include <console/console.h>
 #include <arch/acpi.h>
+#include <arch/io.h>
 #include <arch/stages.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/bist.h>
@@ -78,6 +79,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		prepare_for_resume();
 	}
 
+	if (s3resume || acpi_is_wakeup_s4()) {
+		outb(0xEE, PM_INDEX);
+		outb(0x8, PM_DATA);
+	}
+
 	post_code(0x50);
 	copy_and_run();