[coreboot-gerrit] Patch set updated for coreboot: AMD/bettong: Add UART support (WIP)
Zheng Bao (zheng.bao@amd.com)
gerrit at coreboot.org
Thu Nov 5 11:39:19 CET 2015
Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11749
-gerrit
commit 0438c73f04296429b71f1aaa36ef8afbd9d34637
Author: zbao <fishbaozi at gmail.com>
Date: Thu Nov 5 18:34:19 2015 +0800
AMD/bettong: Add UART support (WIP)
The function delay in uart8250mem.c is not enough for hudson.
Need a seprate patch to fix that.
Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb
Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
src/mainboard/amd/bettong/romstage.c | 27 ++++++++++++
src/southbridge/amd/pi/hudson/Kconfig | 16 +++++++
src/southbridge/amd/pi/hudson/Makefile.inc | 5 +++
src/southbridge/amd/pi/hudson/acpi/uart.asl | 65 +++++++++++++++++++++++++++++
src/southbridge/amd/pi/hudson/uart.c | 47 +++++++++++++++++++++
5 files changed, 160 insertions(+)
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index 9f94d7b..81e3812 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -16,6 +16,7 @@
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/stages.h>
+#include <arch/io.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
@@ -23,6 +24,10 @@
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <southbridge/amd/pi/hudson/hudson.h>
+#include <delay.h>
+
+#define ACPI_MMIO_BASE ((void *)0xFED80000)
+#define AOAC_BASE 0x1E00
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -30,6 +35,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_HAVE_ACPI_RESUME
void *resume_backup_memory;
#endif
+#if CONFIG_DRIVERS_UART_8250MEM
+ u8 byte;
+ msr_t msr;
+#endif
amd_initmmio();
@@ -39,6 +48,24 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x30);
post_code(0x31);
+#if CONFIG_DRIVERS_UART_8250MEM
+ msr = rdmsr(0x1B);
+ msr.lo |= 1 << 11;
+ wrmsr(0x1B, msr);
+ byte = read8(ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2);
+ byte |= 1 << 3;
+ write8(ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2, byte);
+ byte = read8(ACPI_MMIO_BASE + AOAC_BASE + 0x62);
+ byte |= 1 << 3;
+ write8(ACPI_MMIO_BASE + AOAC_BASE + 0x62, byte);
+ write8(ACPI_MMIO_BASE + 0xD00 + 0x89, 0);
+ write8(ACPI_MMIO_BASE + 0xD00 + 0x8A, 0);
+ write8(ACPI_MMIO_BASE + 0xD00 + 0x8E, 0);
+ write8(ACPI_MMIO_BASE + 0xD00 + 0x8F, 0);
+
+ udelay(2000);
+ write8((void *)0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88, 0x01); /* reset UART */
+#endif
console_init();
}
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig
index c720791..94a313d 100644
--- a/src/southbridge/amd/pi/hudson/Kconfig
+++ b/src/southbridge/amd/pi/hudson/Kconfig
@@ -227,3 +227,19 @@ config AZ_PIN
bit 5,4 - pin 2
bit 7,6 - pin 3
endif
+
+config HUDSON_UART
+ bool "UART controller on Kern."
+ default n
+ depends on SOUTHBRIDGE_AMD_PI_KERN
+ select DRIVERS_UART_8250MEM
+ select DRIVERS_UART_8250MEM_32
+ select NO_UART_ON_SUPERIO
+ help
+ There are two UART controllers in Kern.
+ The UART registers are memory-mapped. UART
+ controller 0 registers range from FEDC_6000h
+ to FEDC_6FFFh. UART controller 1 registers
+ range from FEDC_8000h to FEDC_8FFFh.
+
+
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index 00d150f..2c2458c 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -50,6 +50,11 @@ romstage-y += imc.c
ramstage-y += imc.c
endif
+ifeq ($(CONFIG_HUDSON_UART), y)
+romstage-y += uart.c
+ramstage-y += uart.c
+endif
+
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c
diff --git a/src/southbridge/amd/pi/hudson/acpi/uart.asl b/src/southbridge/amd/pi/hudson/acpi/uart.asl
new file mode 100644
index 0000000..ae7baa4
--- /dev/null
+++ b/src/southbridge/amd/pi/hudson/acpi/uart.asl
@@ -0,0 +1,65 @@
+ Scope(\_SB.FUR0)
+ {
+ Device(UART)
+ {
+ Name(_HID, "UTK0001")
+ Name(_CID, "UARTTest")
+ Name(_UID, Zero)
+ Method(_CRS, 0, NotSerialized)
+ {
+ Name(RBUF, Buffer(0x22)
+ {
+ 0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35,
+ 0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00,
+ 0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F,
+ 0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x30, 0x00,
+ 0x79, 0x00
+ })
+ Return(RBUF)
+ }
+ Method(_STA, 0, NotSerialized)
+ {
+ If(LEqual(MWTT, Zero))
+ {
+ Return(0x0F)
+ }
+ Else
+ {
+ Return(Zero)
+ }
+ }
+ }
+ }
+/*
+ Scope(\_SB.FUR1)
+ {
+ Device(UART)
+ {
+ Name(_HID, "UTK0001")
+ Name(_CID, "UARTTest")
+ Name(_UID, One)
+ Method(_CRS, 0, NotSerialized)
+ {
+ Name(RBUF, Buffer(0x22)
+ {
+ 0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35,
+ 0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00,
+ 0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F,
+ 0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x31, 0x00,
+ 0x79, 0x00
+ })
+ Return(RBUF)
+ }
+ Method(_STA, 0, NotSerialized)
+ {
+ If(LEqual(MWTT, Zero))
+ {
+ Return(0x0F)
+ }
+ Else
+ {
+ Return(Zero)
+ }
+ }
+ }
+ }
diff --git a/src/southbridge/amd/pi/hudson/uart.c b/src/southbridge/amd/pi/hudson/uart.c
new file mode 100644
index 0000000..ba35fbf
--- /dev/null
+++ b/src/southbridge/amd/pi/hudson/uart.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+
+#include <boot/coreboot_tables.h>
+#include <console/console.h> /* for __console definition */
+#include <console/uart.h>
+#include <drivers/uart/uart8250reg.h>
+
+#define ACPI_MMIO_BASE 0xFED80000
+#define AOAC_BASE 0x1E00
+uintptr_t uart_platform_base(int idx)
+{
+ return (uintptr_t)(0xFEDC6000 + 0x2000 * (idx & 1));
+}
+
+unsigned int uart_platform_refclk(void)
+{
+ return 48000000;
+}
+
+#ifdef __PRE_RAM__
+void uart_fill_lb(void *data)
+{
+ struct lb_serial serial;
+ serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+ serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
+ serial.baud = default_baudrate();
+ serial.regwidth = 4;
+ lb_add_serial(&serial, data);
+
+ lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}
+#endif
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