[coreboot-gerrit] New patch to review for coreboot: nvidia/tegra210: lp0_resume: clear the MC_INTSTATUS if MC_INTMASK was 0

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12321

-gerrit

commit 9a54d7b30b714b16a3e04347c5f8bebcde3ef4db
Author: Joseph Lo <josephl at nvidia.com>
Date:   Wed Oct 28 15:34:22 2015 +0800

    nvidia/tegra210: lp0_resume: clear the MC_INTSTATUS if MC_INTMASK was 0
    
    The MC/SMMU should be resumed by the kernel. And the unexpected value
    in the MC_INTSTATUS should be cleared before that. Or it will cause
    some noisy MC interrupt once we enable the IRQ in the kernel.
    
    BUG=chrome-os-partner:46796
    BRANCH=none
    TEST=LP0 suspend/resume test and the EMEM decode/arbitration errors
         should not be observed on resume.
    
    Change-Id: I5b32fa58ebcb8e7db6ffc88e13cca050753f621a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 07cb719caf40b59c5519fcf212c2fb50f006812e
    Original-Change-Id: I4d34905c04effd54d0d0edf8809e192283db2ca3
    Original-Signed-off-by: Joseph Lo <josephl at nvidia.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/309248
    Original-Reviewed-by: Tom Warren <twarren at nvidia.com>
    Original-Reviewed-by: Andrew Bresticker <abrestic at chromium.org>
    Original-Commit-Queue: Joseph Lo <yushun.lo at gmail.com>
    Original-Tested-by: Joseph Lo <yushun.lo at gmail.com>
    Original-(cherry picked from commit 13cbcaf441bd762af9cf00eff24eb7709db38d95)
    Original-Signed-off-by: Joseph Lo <josephl at nvidia.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/309497
    Original-Commit-Ready: Andrew Bresticker <abrestic at chromium.org>
---
 src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
index 000d48d..15477d6 100644
--- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
@@ -335,6 +335,8 @@ enum {
 static uint32_t *pmc_set_sw_clamp_ptr = (void *)(PMC_CTLR_BASE + 0x47c);
 
 /* Memory controller registers. */
+static uint32_t *mc_intstatus_ptr = (void *)(MC_CTLR_BASE);
+static uint32_t *mc_intmask_ptr = (void *)(MC_CTLR_BASE + 0x4);
 static uint32_t *mc_video_protect_size_mb_ptr = (void *)(MC_CTLR_BASE + 0x64c);
 
 static uint32_t *mc_video_protect_reg_ctrl_ptr =
@@ -979,6 +981,13 @@ void lp0_resume(void)
 	write32(pmc_dpd_sample_ptr, 0);
 	udelay(10);
 
+	/* Clear the MC_INTSTATUS if MC_INTMASK was 0. */
+	if (!read32(mc_intmask_ptr)) {
+		uint32_t mc_intst_val = read32(mc_intstatus_ptr);
+		if (mc_intst_val)
+			write32(mc_intstatus_ptr, mc_intst_val);
+	}
+
 	/*
 	 * Set both _ACCESS bits so that kernel/secure code
 	 * can reconfig VPR careveout as needed from the TrustZone.