[coreboot-gerrit] New patch to review for coreboot: ultra40m2: remove some probably-useless cargo cult GPIO configuration

[Jonathan A. Kollasch (jakllsch@kollasch.net)]

Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12313

-gerrit

commit e39ccb5f9fe4a7dd931b534d5062ea9fd3835b41
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Tue Nov 3 12:31:52 2015 -0600

    ultra40m2: remove some probably-useless cargo cult GPIO configuration
    
    Change-Id: Ie7ab1ae49f5c9e42dbfe491da05e0fb09692a513
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
---
 src/mainboard/sunw/ultra40m2/romstage.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c
index 8fc8304..c20d39f 100644
--- a/src/mainboard/sunw/ultra40m2/romstage.c
+++ b/src/mainboard/sunw/ultra40m2/romstage.c
@@ -61,8 +61,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+61, 0xf0, 0x05,/* GPIO62 Firewire OHCI disable (active low)? */
 
 #include <southbridge/nvidia/mcp55/early_setup_ss.h>