[coreboot-gerrit] New patch to review for coreboot: ultra40m2: enable on-board IEEE1394 OHCI

[Jonathan A. Kollasch (jakllsch@kollasch.net)]

Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12307

-gerrit

commit 1975ddc763cca470073c4da4f7032cdeac4eafe9
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Tue Nov 3 12:09:50 2015 -0600

    ultra40m2: enable on-board IEEE1394 OHCI
    
    Change-Id: Ibac950d9bcf7210f616398393c68f6d1b22565b8
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
---
 src/mainboard/sunw/ultra40m2/romstage.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c
index d225f59..8fc8304 100644
--- a/src/mainboard/sunw/ultra40m2/romstage.c
+++ b/src/mainboard/sunw/ultra40m2/romstage.c
@@ -62,7 +62,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
-	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ \
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+61, 0xf0, 0x05,/* GPIO62 Firewire OHCI disable (active low)? */
 
 #include <southbridge/nvidia/mcp55/early_setup_ss.h>
 #include "southbridge/nvidia/mcp55/early_setup_car.c"