[coreboot-gerrit] Patch set updated for coreboot: efb2bd9 AGESA: Split S3 backup in CBMEM
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Tue May 26 21:39:27 CEST 2015
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10316
-gerrit
commit efb2bd99b2208bc2e6c06a26969b971b3849517d
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue May 26 10:12:45 2015 +0300
AGESA: Split S3 backup in CBMEM
Use separate CBMEM allocations for stack and heap on S3 resume path.
The allocation of HIGH_SCRATCH_MEMORY is specific to AGESA and is moved
out of globals and ACPI. This region is a replacement for BIOS_HEAP_SIZE
used on non-resume paths.
Change-Id: I6658ce1c06964de5cf13b4e3c84d571f46ce76f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/arch/x86/boot/acpi.c | 3 ---
src/cpu/amd/agesa/family14/Kconfig | 5 -----
src/cpu/amd/agesa/family15rl/Kconfig | 5 -----
src/cpu/amd/agesa/family15tn/Kconfig | 5 -----
src/cpu/amd/agesa/family16kb/Kconfig | 5 -----
src/cpu/amd/agesa/heapmanager.c | 12 ++++++++----
src/cpu/amd/agesa/s3_resume.c | 10 ++++------
src/cpu/amd/agesa/s3_resume.h | 12 ++++++++++++
src/include/cbmem.h | 7 -------
src/northbridge/amd/agesa/BiosCallOuts.h | 2 --
src/northbridge/amd/agesa/oem_s3.c | 7 +++++++
11 files changed, 31 insertions(+), 42 deletions(-)
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index bc2a0cc..669af97 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -917,9 +917,6 @@ void acpi_prepare_resume_backup(void)
if (HIGH_MEMORY_SAVE)
cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE);
-
- if (HIGH_MEMORY_SCRATCH)
- cbmem_add(CBMEM_ID_RESUME_SCRATCH, HIGH_MEMORY_SCRATCH);
}
static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp)
diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig
index 0cf5089..5ef9295 100644
--- a/src/cpu/amd/agesa/family14/Kconfig
+++ b/src/cpu/amd/agesa/family14/Kconfig
@@ -40,9 +40,4 @@ config XIP_ROM_SIZE
hex
default 0x80000
-config HIGH_SCRATCH_MEMORY_SIZE
- hex
- # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
- default 0x71000
-
endif
diff --git a/src/cpu/amd/agesa/family15rl/Kconfig b/src/cpu/amd/agesa/family15rl/Kconfig
index 73b6976..6524118 100644
--- a/src/cpu/amd/agesa/family15rl/Kconfig
+++ b/src/cpu/amd/agesa/family15rl/Kconfig
@@ -41,9 +41,4 @@ config XIP_ROM_SIZE
hex
default 0x100000
-config HIGH_SCRATCH_MEMORY_SIZE
- hex
- # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
- default 0xA1000
-
endif # CPU_AMD_AGESA_FAMILY15_RL
diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig
index e53a988..8e274a3 100644
--- a/src/cpu/amd/agesa/family15tn/Kconfig
+++ b/src/cpu/amd/agesa/family15tn/Kconfig
@@ -40,9 +40,4 @@ config XIP_ROM_SIZE
hex
default 0x100000
-config HIGH_SCRATCH_MEMORY_SIZE
- hex
- # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
- default 0xA1000
-
endif
diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig
index 5f183df..f7e87f7 100644
--- a/src/cpu/amd/agesa/family16kb/Kconfig
+++ b/src/cpu/amd/agesa/family16kb/Kconfig
@@ -44,11 +44,6 @@ config XIP_ROM_SIZE
hex
default 0x100000
-config HIGH_SCRATCH_MEMORY_SIZE
- hex
- # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
- default 0xA1000
-
config FORCE_AM1_SOCKET_SUPPORT
bool
default n
diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/cpu/amd/agesa/heapmanager.c
index bfe8b29..b3af18c 100644
--- a/src/cpu/amd/agesa/heapmanager.c
+++ b/src/cpu/amd/agesa/heapmanager.c
@@ -1,21 +1,25 @@
#include "AGESA.h"
#include "amdlib.h"
-#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "heapManager.h"
#include <cbmem.h>
+#include <cpu/amd/agesa/s3_resume.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+
#include <arch/acpi.h>
#include <string.h>
+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && (HIGH_MEMORY_SCRATCH < BIOS_HEAP_SIZE)
+#error Increase HIGH_MEMORY_SCRATCH allocation
+#endif
+
UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader)
{
UINT32 heap = BIOS_HEAP_START_ADDRESS;
if (acpi_is_wakeup_s3())
- heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH) +
- (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE);
- /* himem_heap_base + high_stack_size */
+ heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH);
return heap;
}
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index d882bdf..5e07d7a 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -25,7 +25,6 @@
#include <cpu/x86/cache.h>
#include <cbmem.h>
#include <string.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <halt.h>
#include "s3_resume.h"
@@ -51,12 +50,12 @@ static void *backup_resume(void)
static void move_stack_high_mem(void)
{
- void *high_stack;
+ void *high_stack = cbmem_find(CBMEM_ID_ROMSTAGE_RAM_STACK);
- high_stack = cbmem_find(CBMEM_ID_RESUME_SCRATCH);
- memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR,
- (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE));
+ /* TODO: Make the switch with empty stack instead. */
+ memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE);
+ /* TODO: We only switch stack on BSP. */
__asm__
volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g"
(high_stack - BSP_STACK_BASE_ADDR)
@@ -95,7 +94,6 @@ void prepare_for_resume(void)
post_code(0x62);
printk(BIOS_DEBUG, "Move CAR stack.\n");
move_stack_high_mem();
- printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
post_code(0x63);
disable_cache_as_ram();
diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h
index ce16f7d..97a2a21 100644
--- a/src/cpu/amd/agesa/s3_resume.h
+++ b/src/cpu/amd/agesa/s3_resume.h
@@ -26,4 +26,16 @@ void prepare_for_resume(void);
void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size);
const void *OemS3Saved_MTRR_Storage(void);
+#define BSP_STACK_BASE_ADDR 0x30000
+
+#if 1
+/* This covers node 0 only. */
+#define HIGH_ROMSTAGE_STACK_SIZE (0x48000 - BSP_STACK_BASE_ADDR)
+#else
+/* This covers total of 8 nodes. */
+#define HIGH_ROMSTAGE_STACK_SIZE (0xA0000 - BSP_STACK_BASE_ADDR)
+#endif
+
+#define HIGH_MEMORY_SCRATCH 0x30000
+
#endif
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index a8ab3cd..5fd67af 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -28,13 +28,6 @@
#define HIGH_MEMORY_SAVE 0
#endif
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
- defined(CONFIG_HIGH_SCRATCH_MEMORY_SIZE)
-#define HIGH_MEMORY_SCRATCH CONFIG_HIGH_SCRATCH_MEMORY_SIZE
-#else
-#define HIGH_MEMORY_SCRATCH 0
-#endif
-
/* Delegation of resume backup memory so we don't have to
* (slowly) handle backing up OS memory in romstage.c
*/
diff --git a/src/northbridge/amd/agesa/BiosCallOuts.h b/src/northbridge/amd/agesa/BiosCallOuts.h
index 64f1cd5..cfe1852 100644
--- a/src/northbridge/amd/agesa/BiosCallOuts.h
+++ b/src/northbridge/amd/agesa/BiosCallOuts.h
@@ -30,13 +30,11 @@
#define BIOS_HEAP_START_ADDRESS 0x010000000
#define BIOS_HEAP_SIZE 0x30000
-#define BSP_STACK_BASE_ADDR 0x30000
#else
#define BIOS_HEAP_START_ADDRESS 0x10000 /* HEAP during cold boot */
#define BIOS_HEAP_SIZE 0x20000
-#define BSP_STACK_BASE_ADDR 0x30000
#endif
diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c
index 08f68e5..779e28b 100644
--- a/src/northbridge/amd/agesa/oem_s3.c
+++ b/src/northbridge/amd/agesa/oem_s3.c
@@ -20,6 +20,7 @@
#include <spi-generic.h>
#include <spi_flash.h>
#include <string.h>
+#include <cbmem.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/agesawrapper.h>
@@ -133,6 +134,12 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams)
u32 MTRRStorageSize = 0;
u32 pos, size;
+ if (HIGH_ROMSTAGE_STACK_SIZE)
+ cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE);
+
+ if (HIGH_MEMORY_SCRATCH)
+ cbmem_add(CBMEM_ID_RESUME_SCRATCH, HIGH_MEMORY_SCRATCH);
+
/* To be consumed in AmdInitResume. */
get_s3nv_data(S3DataTypeNonVolatile, &pos, &size);
if (size && dataBlock->NvStorageSize)
More information about the coreboot-gerrit
mailing list