[coreboot-gerrit] New patch to review for coreboot: a8ddb7c binaryPI boards: Minor fixups to unify boards
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Sat May 23 13:58:56 CEST 2015
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10284
-gerrit
commit a8ddb7ca9ba7e8a3b01d40246de60785861b944d
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Sat May 23 14:19:11 2015 +0300
binaryPI boards: Minor fixups to unify boards
Some missing static declarations and whitespace on the console.
Change-Id: I1af59dbfb1396297bd671b43d9326dffdd7f59d4
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/amd/lamar/BiosCallOuts.c | 6 +++---
src/mainboard/amd/lamar/PlatformGnbPcie.c | 4 ++--
src/mainboard/amd/olivehillplus/BiosCallOuts.c | 2 +-
src/mainboard/amd/olivehillplus/PlatformGnbPcie.c | 6 +++---
src/mainboard/amd/olivehillplus/acpi/sleep.asl | 6 ++++--
src/mainboard/biostar/am1ml/BiosCallOuts.c | 4 ++--
6 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c
index 7728663..24689d2 100644
--- a/src/mainboard/amd/lamar/BiosCallOuts.c
+++ b/src/mainboard/amd/lamar/BiosCallOuts.c
@@ -300,7 +300,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
- printk(BIOS_DEBUG, "\nFch OEM config in INIT RESET\n");
+ printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
//FchParams->EcChannel0 = TRUE; /* logical devicd 3 */
FchParams->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
@@ -317,7 +317,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
} else if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
- printk(BIOS_DEBUG, "Fch OEM config in INIT ENV");
+ printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
/* Turn on FCH GPP slots */
FchParams->Gpp.GppFunctionEnable = TRUE;
@@ -337,7 +337,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
/* Fan Control */
oem_fan_control(FchParams);
}
- printk(BIOS_DEBUG, " Done\n");
+ printk(BIOS_DEBUG, "Done\n");
return AGESA_SUCCESS;
}
diff --git a/src/mainboard/amd/lamar/PlatformGnbPcie.c b/src/mainboard/amd/lamar/PlatformGnbPcie.c
index a6928de..fd45908 100644
--- a/src/mainboard/amd/lamar/PlatformGnbPcie.c
+++ b/src/mainboard/amd/lamar/PlatformGnbPcie.c
@@ -22,7 +22,7 @@
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
-const PCIe_PORT_DESCRIPTOR PortList [] = {
+static const PCIe_PORT_DESCRIPTOR PortList [] = {
/*
* Lanes to pins to PCI device mapping can be found in section 2.12 of the
@@ -107,7 +107,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = {
},
};
-const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
.Flags = DESCRIPTOR_TERMINATE_LIST,
.SocketId = 0,
.PciePortList = PortList,
diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c
index dbd91a4..62e2e09 100644
--- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c
+++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c
@@ -266,7 +266,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
- printk(BIOS_DEBUG, "\nFch OEM config in INIT RESET\n");
+ printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
FchParams->FchReset.SataEnable = hudson_sata_enable();
diff --git a/src/mainboard/amd/olivehillplus/PlatformGnbPcie.c b/src/mainboard/amd/olivehillplus/PlatformGnbPcie.c
index 7ebd1a5..46a20da 100644
--- a/src/mainboard/amd/olivehillplus/PlatformGnbPcie.c
+++ b/src/mainboard/amd/olivehillplus/PlatformGnbPcie.c
@@ -21,7 +21,7 @@
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
-const PCIe_PORT_DESCRIPTOR PortList [] = {
+static const PCIe_PORT_DESCRIPTOR PortList [] = {
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
@@ -73,7 +73,7 @@ const PCIe_PORT_DESCRIPTOR PortList [] = {
}
};
-const PCIe_DDI_DESCRIPTOR DdiList [] = {
+static const PCIe_DDI_DESCRIPTOR DdiList [] = {
/* DP0 to HDMI0/DP */
{
0,
@@ -94,7 +94,7 @@ const PCIe_DDI_DESCRIPTOR DdiList [] = {
},
};
-const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
.Flags = DESCRIPTOR_TERMINATE_LIST,
.SocketId = 0,
.PciePortList = PortList,
diff --git a/src/mainboard/amd/olivehillplus/acpi/sleep.asl b/src/mainboard/amd/olivehillplus/acpi/sleep.asl
index 1e6221e..7085e4b 100644
--- a/src/mainboard/amd/olivehillplus/acpi/sleep.asl
+++ b/src/mainboard/amd/olivehillplus/acpi/sleep.asl
@@ -26,7 +26,7 @@ Name(WKST,Package(){Zero, Zero})
* Entry:
* Arg0=The value of the sleeping state S1=1, S2=2, etc
*
-*s Exit:
+* Exit:
* -none-
*
* The _PTS control method is executed at the beginning of the sleep process
@@ -89,7 +89,9 @@ Method(\_WAK, 1) {
/* DBGO("From S") */
/* DBGO(Arg0) */
/* DBGO(" to S0\n") */
- Store(1,USBS)
+
+ /* clear USB wake up signal */
+ Store(1, USBS)
\_SB.AWAK(Arg0)
diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c
index d8924d8..5f644e7 100644
--- a/src/mainboard/biostar/am1ml/BiosCallOuts.c
+++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c
@@ -116,7 +116,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
- printk(BIOS_DEBUG, "Fch OEM config in INIT RESET \n");
+ printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams_reset->FchReset.Xhci1Enable = FALSE;
FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
@@ -124,7 +124,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
FchParams_reset->FchReset.IdeEnable = 0;
} else if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
- printk(BIOS_DEBUG, "Fch OEM config in INIT ENV\n");
+ printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
/* Azalia Controller OEM Codec Table Pointer */
FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST*)(&CodecTableList[0]);
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