[coreboot-gerrit] Patch set updated for coreboot: 95f9998 x201: Add TPM declaration.

Vladimir Serbinenko (phcoder@gmail.com) gerrit at coreboot.org
Thu May 21 20:52:31 CEST 2015


Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10278

-gerrit

commit 95f999880f6b8993a69bd8328fa66d29308d3556
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date:   Thu May 21 09:28:14 2015 +0200

    x201: Add TPM declaration.
    
    This allows to deactivate TPM on X201.
    
    Change-Id: Ic085db6cc2c57668e7a4fdbc7440735c806cc256
    Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
 src/mainboard/lenovo/x201/Kconfig       | 1 +
 src/mainboard/lenovo/x201/devicetree.cb | 3 +++
 src/mainboard/lenovo/x201/dsdt.asl      | 8 ++++++++
 src/mainboard/lenovo/x201/romstage.c    | 5 +++++
 4 files changed, 17 insertions(+)

diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig
index 93bfb02..7f96cbe 100644
--- a/src/mainboard/lenovo/x201/Kconfig
+++ b/src/mainboard/lenovo/x201/Kconfig
@@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
 	select SUPERIO_NSC_PC87382
 	select DRIVERS_LENOVO_WACOM
+	select MAINBOARD_HAS_LPC_TPM
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index d892926..f87ab10 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -153,6 +153,9 @@ chip northbridge/intel/nehalem
 					# DLPC, not connected
 					device pnp 164e.19 off end
 				end
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
 			end
 			device pci 1f.2 on # IDE/SATA
 				subsystemid 0x17aa 0x2168
diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl
index 20d647e..dab66e4 100644
--- a/src/mainboard/lenovo/x201/dsdt.asl
+++ b/src/mainboard/lenovo/x201/dsdt.asl
@@ -87,6 +87,14 @@ DefinitionBlock(
 		}
 	}
 
+/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+       #include <drivers/pc80/tpm/acpi/tpm.asl>
+}
+
 	/* Chipset specific sleep states */
 	#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
 
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 8d12890..1e335d3 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -37,6 +37,7 @@
 #include <timestamp.h>
 #include <arch/acpi.h>
 #include <cbmem.h>
+#include <tpm.h>
 
 #include "gpio.h"
 #include "dock.h"
@@ -306,5 +307,9 @@ void main(unsigned long bist)
 	}
 #endif
 
+#if CONFIG_LPC_TPM
+	init_tpm(s3resume);
+#endif
+
 	timestamp_add_now(TS_END_ROMSTAGE);
 }



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