[coreboot-gerrit] Patch set updated for coreboot: c0de705 sandybridge native: Add call to TPM code.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Thu May 21 20:49:19 CEST 2015
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10272
-gerrit
commit c0de705cbbf8052f17a7a71323432f44d92cdddb
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Mon May 18 10:31:35 2015 +0200
sandybridge native: Add call to TPM code.
This allows to deactivate TPM on boards using native sandy/ivy init.
Change-Id: I9455179c7b51097a3a9554c16a407365fbc65e6f
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/northbridge/intel/sandybridge/romstage_native.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c
index 332d9ba..84c2f58 100644
--- a/src/northbridge/intel/sandybridge/romstage_native.c
+++ b/src/northbridge/intel/sandybridge/romstage_native.c
@@ -32,6 +32,7 @@
#include <device/pci_def.h>
#include <device/device.h>
#include <halt.h>
+#include <tpm.h>
#include "raminit_native.h"
#include <northbridge/intel/sandybridge/chip.h>
#include "southbridge/intel/bd82x6x/pch.h"
@@ -129,6 +130,10 @@ void main(unsigned long bist)
northbridge_romstage_finalize(s3resume);
+#if CONFIG_LPC_TPM
+ init_tpm(s3resume);
+#endif
+
post_code(0x3f);
timestamp_add_now(TS_END_ROMSTAGE);
}
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