[coreboot-gerrit] New patch to review for coreboot: 33b7b72 x230: Add TPM declaration.

[Vladimir Serbinenko (phcoder@gmail.com)]

Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10273

-gerrit

commit 33b7b72cfbdd34e4174f53b6b490c07af72d74bb
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date:   Wed May 13 17:47:58 2015 +0200

    x230: Add TPM declaration.
    
    This allows to deactivate TPM on X230.
    
    Change-Id: I73d4272da62335ec3766ce4814d5b46538b190fe
    Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
 src/mainboard/lenovo/x230/Kconfig       | 1 +
 src/mainboard/lenovo/x230/devicetree.cb | 4 ++++
 src/mainboard/lenovo/x230/dsdt.asl      | 8 ++++++++
 3 files changed, 13 insertions(+)

diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
index 05b7506..1551e27 100644
--- a/src/mainboard/lenovo/x230/Kconfig
+++ b/src/mainboard/lenovo/x230/Kconfig
@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
 	select IVYBRIDGE_LVDS
 	select DRIVERS_RICOH_RCE822
+	select MAINBOARD_HAS_LPC_TPM
 
 	# Workaround for EC/KBC IRQ1.
 	select SERIRQ_CONTINUOUS_MODE
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index 55677a3..c8274e2 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -128,6 +128,10 @@ chip northbridge/intel/sandybridge
 					register "dock_event_enable" = "0x01"
 				end
 
+				chip drivers/pc80/tpm
+				     device pnp 0c31.0 on end
+				end
+
 				chip ec/lenovo/h8
 					device pnp ff.2 on # dummy
 						io 0x60 = 0x62
diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl
index 85e2b4f..7db79af 100644
--- a/src/mainboard/lenovo/x230/dsdt.asl
+++ b/src/mainboard/lenovo/x230/dsdt.asl
@@ -50,6 +50,14 @@ DefinitionBlock(
 			#include <southbridge/intel/bd82x6x/acpi/pch.asl>
 		}
 	}
+/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+	#include <drivers/pc80/tpm/acpi/tpm.asl>
+}
+
 
 	/* Chipset specific sleep states */
 	#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>