[coreboot-gerrit] Patch set updated for coreboot: 3781c4b x86: fix mirror_payload()

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10260

-gerrit

commit 3781c4b16c9734ecb4815806bd3cc86eca01e410
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue May 19 16:32:54 2015 -0500

    x86: fix mirror_payload()
    
    The api to mirror_payload() was changed, but as no board
    in coreboot.org selected MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING
    this issue was missed. Update to using the prog functions.
    
    Change-Id: I4037f5dc6059c0707e1bf38eb1fa3d1bbb408e2a
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/cpu/x86/mirror_payload.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/cpu/x86/mirror_payload.c b/src/cpu/x86/mirror_payload.c
index 0ba8d05..6a970f6 100644
--- a/src/cpu/x86/mirror_payload.c
+++ b/src/cpu/x86/mirror_payload.c
@@ -24,7 +24,7 @@
 #include <bootmem.h>
 #include <program_loading.h>
 
-void mirror_payload(struct payload *payload)
+void mirror_payload(struct prog *payload)
 {
 	char *buffer;
 	size_t size;
@@ -34,8 +34,8 @@ void mirror_payload(struct payload *payload)
 	const uintptr_t intra_cacheline_mask = cacheline_size - 1;
 	const uintptr_t cacheline_mask = ~intra_cacheline_mask;
 
-	src = payload->backing_store.data;
-	size = payload->backing_store.size;
+	src = prog_start(payload);
+	size = prog_size(payload);
 
 	/*
 	 * Adjust size so that the start and end points are aligned to a
@@ -67,5 +67,5 @@ void mirror_payload(struct payload *payload)
 	memcpy(buffer, src, size);
 
 	/* Update the payload's backing store. */
-	payload->backing_store.data = &buffer[alignment_diff];
+	prog_set_area(payload, &buffer[alignment_diff], prog_size(payload));
 }